clk: Ingenic: Remove unnecessary spinlock when reading registers.

	const struct ingenic_cgu_pll_info *pll_info;

	unsigned m, n, od_enc, od;

	bool bypass;

	unsigned long flags;

	u32 ctl;

	clk_info = &cgu->clock_info[ingenic_clk->idx];

	BUG_ON(clk_info->type != CGU_CLK_PLL);

	pll_info = &clk_info->pll;

	spin_lock_irqsave(&cgu->lock, flags);

	ctl = readl(cgu->base + pll_info->reg);

	spin_unlock_irqrestore(&cgu->lock, flags);

	m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0);

	m += pll_info->m_offset;

	struct ingenic_cgu *cgu = ingenic_clk->cgu;

	const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);

	const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;

	unsigned long flags;

	u32 ctl;

	spin_lock_irqsave(&cgu->lock, flags);

	ctl = readl(cgu->base + pll_info->reg);

	spin_unlock_irqrestore(&cgu->lock, flags);

	return !!(ctl & BIT(pll_info->enable_bit));

}

	struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);

	struct ingenic_cgu *cgu = ingenic_clk->cgu;

	const struct ingenic_cgu_clk_info *clk_info;

	unsigned long flags;

	int enabled = 1;

	clk_info = &cgu->clock_info[ingenic_clk->idx];

	if (clk_info->type & CGU_CLK_GATE) {

		spin_lock_irqsave(&cgu->lock, flags);

	if (clk_info->type & CGU_CLK_GATE)

		enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate);

		spin_unlock_irqrestore(&cgu->lock, flags);

	}

	return enabled;

}