net: stmmac: fix enabling socfpga's ptp_ref_clock (15ce3060) · Commits · 戴 / test

There are 2 registers to write to enable a ptp ref clock coming from the fpga. One that enables the usage of the clock from the fpga for emac0 and emac1 as a ptp ref clock, and the other to allow signals from the fpga to reach emac0 and emac1. Currently, if the dwmac-socfpga has phymode set to PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_GMII, or PHY_INTERFACE_MODE_SGMII, both registers will be written and the ptp ref clock will be set as coming from the fpga. Separate the 2 register writes to only enable signals from the fpga to reach emac0 or emac1 when ptp ref clock is not coming from the fpga. Signed-off-by:

Julien Beraud <julien.beraud@orolia.com> Signed-off-by:

David S. Miller <davem@davemloft.net>

drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

+6 −3

Original line number	Diff line number	Diff line
		@@ -291,16 +291,19 @@ static int socfpga_gen5_set_phy_mode(struct socfpga_dwmac *dwmac)
		phymode == PHY_INTERFACE_MODE_MII \|\|
		phymode == PHY_INTERFACE_MODE_GMII \|\|
		phymode == PHY_INTERFACE_MODE_SGMII) {
		ctrl \|= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
		regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
		&module);
		module \|= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2));
		regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
		module);
		} else {
		ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2));
		}

		if (dwmac->f2h_ptp_ref_clk)
		ctrl \|= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
		else
		ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK <<
		(reg_shift / 2));

		regmap_write(sys_mgr_base_addr, reg_offset, ctrl);

		/* Deassert reset for the phy configuration to be sampled by

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