Commit 15a1ff30 authored by Laurent Pinchart's avatar Laurent Pinchart Committed by Simon Horman
Browse files

ARM: dts: r8a7790: Convert to new LVDS DT bindings 



The internal LVDS encoder now has DT bindings separate from the DU. Port
the device tree over to the new model.

Fixes: c6a27fa4 ("drm: rcar-du: Convert LVDS encoder code to bridge driver")
Fixes: 4bdb7aa7 ("ARM: dts: r8a7790: add soc node")
Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: default avatarNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 60cc43fc

arch/arm/boot/dts/r8a7790-lager.dts

+17 −5
Original line number Diff line number Diff line
@@ -379,7 +379,7 @@ 
				port@0 {

					reg = <0>;

					adv7511_in: endpoint {

						remote-endpoint = <&du_out_lvds0>;

						remote-endpoint = <&lvds0_out>;

					};

				};
@@ -467,10 +467,8 @@ 
	status = "okay";



	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,

		 <&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>,

		 <&x13_clk>, <&x2_clk>;

	clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1",

		      "dclkin.0", "dclkin.1";

	clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1";



	ports {

		port@0 {
@@ -478,12 +476,26 @@ 
				remote-endpoint = <&adv7123_in>;

			};

		};

	};

};



&lvds0 {

	status = "okay";



	ports {

		port@1 {

			endpoint {

				remote-endpoint = <&adv7511_in>;

			};

		};

		port@2 {

	};

};



&lvds1 {

	status = "okay";



	ports {

		port@1 {

			lvds_connector: endpoint {

			};

		};

arch/arm/boot/dts/r8a7790.dtsi

+57 −8
Original line number Diff line number Diff line
@@ -1627,18 +1627,13 @@ 


		du: display@feb00000 {

			compatible = "renesas,du-r8a7790";

			reg = <0 0xfeb00000 0 0x70000>,

			      <0 0xfeb90000 0 0x1c>,

			      <0 0xfeb94000 0 0x1c>;

			reg-names = "du", "lvds.0", "lvds.1";

			reg = <0 0xfeb00000 0 0x70000>;

			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,

				 <&cpg CPG_MOD 722>, <&cpg CPG_MOD 726>,

				 <&cpg CPG_MOD 725>;

			clock-names = "du.0", "du.1", "du.2", "lvds.0",

				      "lvds.1";

				 <&cpg CPG_MOD 722>;

			clock-names = "du.0", "du.1", "du.2";

			status = "disabled";



			ports {
@@ -1653,11 +1648,65 @@ 
				port@1 {

					reg = <1>;

					du_out_lvds0: endpoint {

						remote-endpoint = <&lvds0_in>;

					};

				};

				port@2 {

					reg = <2>;

					du_out_lvds1: endpoint {

						remote-endpoint = <&lvds1_in>;

					};

				};

			};

		};



		lvds0: lvds@feb90000 {

			compatible = "renesas,r8a7790-lvds";

			reg = <0 0xfeb90000 0 0x1c>;

			clocks = <&cpg CPG_MOD 726>;

			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;

			resets = <&cpg 726>;

			status = "disabled";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

					lvds0_in: endpoint {

						remote-endpoint = <&du_out_lvds0>;

					};

				};

				port@1 {

					reg = <1>;

					lvds0_out: endpoint {

					};

				};

			};

		};



		lvds1: lvds@feb94000 {

			compatible = "renesas,r8a7790-lvds";

			reg = <0 0xfeb94000 0 0x1c>;

			clocks = <&cpg CPG_MOD 725>;

			power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;

			resets = <&cpg 725>;

			status = "disabled";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

					lvds1_in: endpoint {

						remote-endpoint = <&du_out_lvds1>;

					};

				};

				port@1 {

					reg = <1>;

					lvds1_out: endpoint {

					};

				};

			};

CRA Git | Maintained and supported by SUSTech CRA and CCSE