drm/i915/dpll_mgr: convert to drm_device based logging macros.

	mutex_lock(&dev_priv->dpll_lock);

	drm_WARN_ON(&dev_priv->drm, !pll->state.crtc_mask);

	if (!pll->active_mask) {

		DRM_DEBUG_DRIVER("setting up %s\n", pll->info->name);

		drm_dbg(&dev_priv->drm, "setting up %s\n", pll->info->name);

		drm_WARN_ON(&dev_priv->drm, pll->on);

		assert_shared_dpll_disabled(dev_priv, pll);

	pll->active_mask |= crtc_mask;

	DRM_DEBUG_KMS("enable %s (active %x, on? %d) for crtc %d\n",

	drm_dbg_kms(&dev_priv->drm,

		    "enable %s (active %x, on? %d) for crtc %d\n",

		    pll->info->name, pll->active_mask, pll->on,

		    crtc->base.base.id);

	}

	drm_WARN_ON(&dev_priv->drm, pll->on);

	DRM_DEBUG_KMS("enabling %s\n", pll->info->name);

	drm_dbg_kms(&dev_priv->drm, "enabling %s\n", pll->info->name);

	pll->info->funcs->enable(dev_priv, pll);

	pll->on = true;

	if (drm_WARN_ON(&dev_priv->drm, !(pll->active_mask & crtc_mask)))

		goto out;

	DRM_DEBUG_KMS("disable %s (active %x, on? %d) for crtc %d\n",

	drm_dbg_kms(&dev_priv->drm,

		    "disable %s (active %x, on? %d) for crtc %d\n",

		    pll->info->name, pll->active_mask, pll->on,

		    crtc->base.base.id);

	if (pll->active_mask)

		goto out;

	DRM_DEBUG_KMS("disabling %s\n", pll->info->name);

	drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name);

	pll->info->funcs->disable(dev_priv, pll);

	pll->on = false;

		if (memcmp(pll_state,

			   &shared_dpll[i].hw_state,

			   sizeof(*pll_state)) == 0) {

			DRM_DEBUG_KMS("[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n",

			drm_dbg_kms(&dev_priv->drm,

				    "[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n",

				    crtc->base.base.id, crtc->base.name,

				    pll->info->name,

				    shared_dpll[i].crtc_mask,

	/* Ok no matching timings, maybe there's a free one? */

	if (unused_pll) {

		DRM_DEBUG_KMS("[CRTC:%d:%s] allocated %s\n",

		drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] allocated %s\n",

			    crtc->base.base.id, crtc->base.name,

			    unused_pll->info->name);

		return unused_pll;

			    const struct intel_shared_dpll *pll,

			    const struct intel_dpll_hw_state *pll_state)

{

	struct drm_i915_private *i915 = to_i915(state->base.dev);

	struct intel_shared_dpll_state *shared_dpll;

	const enum intel_dpll_id id = pll->info->id;

	if (shared_dpll[id].crtc_mask == 0)

		shared_dpll[id].hw_state = *pll_state;

	DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->info->name,

	drm_dbg(&i915->drm, "using %s for pipe %c\n", pll->info->name,

		pipe_name(crtc->pipe));

	shared_dpll[id].crtc_mask |= 1 << crtc->pipe;

		i = (enum intel_dpll_id) crtc->pipe;

		pll = &dev_priv->shared_dplls[i];

		DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",

		drm_dbg_kms(&dev_priv->drm,

			    "[CRTC:%d:%s] using pre-allocated %s\n",

			    crtc->base.base.id, crtc->base.name,

			    pll->info->name);

	} else {

static void ibx_dump_hw_state(struct drm_i915_private *dev_priv,

			      const struct intel_dpll_hw_state *hw_state)

{

	DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "

	drm_dbg_kms(&dev_priv->drm,

		    "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "

		    "fp0: 0x%x, fp1: 0x%x\n",

		    hw_state->dpll,

		    hw_state->dpll_md,

		pll_id = DPLL_ID_LCPLL_2700;

		break;

	default:

		DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock);

		drm_dbg_kms(&dev_priv->drm, "Invalid clock for DP: %d\n",

			    clock);

		return NULL;

	}

static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,

			      const struct intel_dpll_hw_state *hw_state)

{

	DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",

	drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",

		    hw_state->wrpll, hw_state->spll);

}

		       intel_de_read(dev_priv, regs[id].ctl) | LCPLL_PLL_ENABLE);

	if (intel_de_wait_for_set(dev_priv, DPLL_STATUS, DPLL_LOCK(id), 5))

		DRM_ERROR("DPLL %d not locked\n", id);

		drm_err(&dev_priv->drm, "DPLL %d not locked\n", id);

}

static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv,

{

	struct intel_crtc_state *crtc_state =

		intel_atomic_get_new_crtc_state(state, crtc);

	struct drm_i915_private *i915 = to_i915(crtc->base.dev);

	struct intel_shared_dpll *pll;

	bool bret;

	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {

		bret = skl_ddi_hdmi_pll_dividers(crtc_state);

		if (!bret) {

			DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");

			drm_dbg_kms(&i915->drm,

				    "Could not get HDMI pll dividers.\n");

			return false;

		}

	} else if (intel_crtc_has_dp_encoder(crtc_state)) {

		bret = skl_ddi_dp_set_dpll_hw_state(crtc_state);

		if (!bret) {

			DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");

			drm_dbg_kms(&i915->drm,

				    "Could not set DP dpll HW state.\n");

			return false;

		}

	} else {

static void skl_dump_hw_state(struct drm_i915_private *dev_priv,

			      const struct intel_dpll_hw_state *hw_state)

{

	DRM_DEBUG_KMS("dpll_hw_state: "

	drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: "

		      "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",

		      hw_state->ctrl1,

		      hw_state->cfgcr1,

		if (wait_for_us((intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) &

				 PORT_PLL_POWER_STATE), 200))

			DRM_ERROR("Power state not set for PLL:%d\n", port);

			drm_err(&dev_priv->drm,

				"Power state not set for PLL:%d\n", port);

	}

	/* Disable 10 bit clock */

	if (wait_for_us((intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),

			200))

		DRM_ERROR("PLL %d not locked\n", port);

		drm_err(&dev_priv->drm, "PLL %d not locked\n", port);

	if (IS_GEMINILAKE(dev_priv)) {

		temp = intel_de_read(dev_priv, BXT_PORT_TX_DW5_LN0(phy, ch));

		if (wait_for_us(!(intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) &

				  PORT_PLL_POWER_STATE), 200))

			DRM_ERROR("Power state not reset for PLL:%d\n", port);

			drm_err(&dev_priv->drm,

				"Power state not reset for PLL:%d\n", port);

	}

}

	hw_state->pcsdw12 = intel_de_read(dev_priv,

					  BXT_PORT_PCS_DW12_LN01(phy, ch));

	if (intel_de_read(dev_priv, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)

		DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",

		drm_dbg(&dev_priv->drm,

			"lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",

			hw_state->pcsdw12,

				 intel_de_read(dev_priv, BXT_PORT_PCS_DW12_LN23(phy, ch)));

			intel_de_read(dev_priv,

				      BXT_PORT_PCS_DW12_LN23(phy, ch)));

	hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;

	ret = true;

bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,

			  struct bxt_clk_div *clk_div)

{

	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct dpll best_clock;

	 * i9xx_crtc_compute_clock

	 */

	if (!bxt_find_best_dpll(crtc_state, &best_clock)) {

		DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",

		drm_dbg(&i915->drm, "no PLL dividers found for clock %d pipe %c\n",

			crtc_state->port_clock,

			pipe_name(crtc->pipe));

		return false;

static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,

				      const struct bxt_clk_div *clk_div)

{

	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);

	struct intel_dpll_hw_state *dpll_hw_state = &crtc_state->dpll_hw_state;

	int clock = crtc_state->port_clock;

	int vco = clk_div->vco;

		gain_ctl = 1;

		targ_cnt = 9;

	} else {

		DRM_ERROR("Invalid VCO\n");

		drm_err(&i915->drm, "Invalid VCO\n");

		return false;

	}

	id = (enum intel_dpll_id) encoder->port;

	pll = intel_get_shared_dpll_by_id(dev_priv, id);

	DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",

	drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] using pre-allocated %s\n",

		    crtc->base.base.id, crtc->base.name, pll->info->name);

	intel_reference_shared_dpll(state, crtc,

static void bxt_dump_hw_state(struct drm_i915_private *dev_priv,

			      const struct intel_dpll_hw_state *hw_state)

{

	DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"

	drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"

		    "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "

		    "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",

		    hw_state->ebb0,

	/* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */

	if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id),

				  PLL_POWER_STATE, 5))

		DRM_ERROR("PLL %d Power not enabled\n", id);

		drm_err(&dev_priv->drm, "PLL %d Power not enabled\n", id);

	/*

	 * 3. Configure DPLL_CFGCR0 to set SSC enable/disable,

	/* 7. Wait for PLL lock status in DPLL_ENABLE. */

	if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5))

		DRM_ERROR("PLL %d not locked\n", id);

		drm_err(&dev_priv->drm, "PLL %d not locked\n", id);

	/*

	 * 8. If the frequency will result in a change to the voltage

	/* 4. Wait for PLL not locked status in DPLL_ENABLE. */

	if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5))

		DRM_ERROR("PLL %d locked\n", id);

		drm_err(&dev_priv->drm, "PLL %d locked\n", id);

	/*

	 * 5. If the frequency will result in a change to the voltage

	/* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */

	if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id),

				    PLL_POWER_STATE, 5))

		DRM_ERROR("PLL %d Power not disabled\n", id);

		drm_err(&dev_priv->drm, "PLL %d Power not disabled\n", id);

}

static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,

{

	struct intel_crtc_state *crtc_state =

		intel_atomic_get_new_crtc_state(state, crtc);

	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);

	struct intel_shared_dpll *pll;

	bool bret;

	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {

		bret = cnl_ddi_hdmi_pll_dividers(crtc_state);

		if (!bret) {

			DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");

			drm_dbg_kms(&i915->drm,

				    "Could not get HDMI pll dividers.\n");

			return false;

		}

	} else if (intel_crtc_has_dp_encoder(crtc_state)) {

		bret = cnl_ddi_dp_set_dpll_hw_state(crtc_state);

		if (!bret) {

			DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");

			drm_dbg_kms(&i915->drm,

				    "Could not set DP dpll HW state.\n");

			return false;

		}

	} else {

		DRM_DEBUG_KMS("Skip DPLL setup for output_types 0x%x\n",

		drm_dbg_kms(&i915->drm,

			    "Skip DPLL setup for output_types 0x%x\n",

			    crtc_state->output_types);

		return false;

	}

				     BIT(DPLL_ID_SKL_DPLL1) |

				     BIT(DPLL_ID_SKL_DPLL0));

	if (!pll) {

		DRM_DEBUG_KMS("No PLL selected\n");

		drm_dbg_kms(&i915->drm, "No PLL selected\n");

		return false;

	}

static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,

			      const struct intel_dpll_hw_state *hw_state)

{

	DRM_DEBUG_KMS("dpll_hw_state: "

	drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: "

		    "cfgcr0: 0x%x, cfgcr1: 0x%x\n",

		    hw_state->cfgcr0,

		    hw_state->cfgcr1);

	if (!icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,

				      pll_state, is_dkl)) {

		DRM_DEBUG_KMS("Failed to find divisors for clock %d\n", clock);

		drm_dbg_kms(&dev_priv->drm,

			    "Failed to find divisors for clock %d\n", clock);

		return false;

	}

		}

		if (m2div_int > 255) {

			DRM_DEBUG_KMS("Failed to find mdiv for clock %d\n",

			drm_dbg_kms(&dev_priv->drm,

				    "Failed to find mdiv for clock %d\n",

				    clock);

			return false;

		}

	unsigned long dpll_mask;

	if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) {

		DRM_DEBUG_KMS("Could not calculate combo PHY PLL state.\n");

		drm_dbg_kms(&dev_priv->drm,

			    "Could not calculate combo PHY PLL state.\n");

		return false;

	}

						&port_dpll->hw_state,

						dpll_mask);

	if (!port_dpll->pll) {

		DRM_DEBUG_KMS("No combo PHY PLL found for [ENCODER:%d:%s]\n",

		drm_dbg_kms(&dev_priv->drm,

			    "No combo PHY PLL found for [ENCODER:%d:%s]\n",

			    encoder->base.base.id, encoder->base.name);

		return false;

	}

	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];

	if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) {

		DRM_DEBUG_KMS("Could not calculate TBT PLL state.\n");

		drm_dbg_kms(&dev_priv->drm,

			    "Could not calculate TBT PLL state.\n");

		return false;

	}

						&port_dpll->hw_state,

						BIT(DPLL_ID_ICL_TBTPLL));

	if (!port_dpll->pll) {

		DRM_DEBUG_KMS("No TBT-ALT PLL found\n");

		drm_dbg_kms(&dev_priv->drm, "No TBT-ALT PLL found\n");

		return false;

	}

	intel_reference_shared_dpll(state, crtc,

	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];

	if (!icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state)) {

		DRM_DEBUG_KMS("Could not calculate MG PHY PLL state.\n");

		drm_dbg_kms(&dev_priv->drm,

			    "Could not calculate MG PHY PLL state.\n");

		goto err_unreference_tbt_pll;

	}

						&port_dpll->hw_state,

						BIT(dpll_id));

	if (!port_dpll->pll) {

		DRM_DEBUG_KMS("No MG PHY PLL found\n");

		drm_dbg_kms(&dev_priv->drm, "No MG PHY PLL found\n");

		goto err_unreference_tbt_pll;

	}

	intel_reference_shared_dpll(state, crtc,

	 * immediate.

	 */

	if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_POWER_STATE, 1))

		DRM_ERROR("PLL %d Power not enabled\n", pll->info->id);

		drm_err(&dev_priv->drm, "PLL %d Power not enabled\n",

			pll->info->id);

}

static void icl_pll_enable(struct drm_i915_private *dev_priv,

	/* Timeout is actually 600us. */

	if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 1))

		DRM_ERROR("PLL %d not locked\n", pll->info->id);

		drm_err(&dev_priv->drm, "PLL %d not locked\n", pll->info->id);

}

static void combo_pll_enable(struct drm_i915_private *dev_priv,

	/* Timeout is actually 1us. */

	if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_LOCK, 1))

		DRM_ERROR("PLL %d locked\n", pll->info->id);

		drm_err(&dev_priv->drm, "PLL %d locked\n", pll->info->id);

	/* DVFS post sequence would be here. See the comment above. */

	 * immediate.

	 */

	if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_POWER_STATE, 1))

		DRM_ERROR("PLL %d Power not disabled\n", pll->info->id);

		drm_err(&dev_priv->drm, "PLL %d Power not disabled\n",

			pll->info->id);

}

static void combo_pll_disable(struct drm_i915_private *dev_priv,

static void icl_dump_hw_state(struct drm_i915_private *dev_priv,

			      const struct intel_dpll_hw_state *hw_state)

{

	DRM_DEBUG_KMS("dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "

	drm_dbg_kms(&dev_priv->drm,

		    "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, "

		    "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, "

		    "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "

		    "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, "

 * @dev_priv: i915 drm device

 * @hw_state: hw state to be written to the log

 *

 * Write the relevant values in @hw_state to dmesg using DRM_DEBUG_KMS.

 * Write the relevant values in @hw_state to dmesg using drm_dbg_kms.

 */

void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,

			      const struct intel_dpll_hw_state *hw_state)

		/* fallback for platforms that don't use the shared dpll

		 * infrastructure

		 */

		DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "

		drm_dbg_kms(&dev_priv->drm,

			    "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "

			    "fp0: 0x%x, fp1: 0x%x\n",

			    hw_state->dpll,

			    hw_state->dpll_md,