Merge tag 'v5.4-rc5' into devel (1566a6a3) · Commits · 戴 / test

.mailmap

+3 −1

Original line number	Diff line number	Diff line
		@@ -196,7 +196,8 @@ Oleksij Rempel <linux@rempel-privat.de> <o.rempel@pengutronix.de>
		Oleksij Rempel <linux@rempel-privat.de> <ore@pengutronix.de>
		Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it>
		Patrick Mochel <mochel@digitalimplant.org>
		Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
		Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
		Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
		Peter A Jonsson <pj@ludd.ltu.se>
		Peter Oruba <peter@oruba.de>
		Peter Oruba <peter.oruba@amd.com>
		@@ -229,6 +230,7 @@ Shuah Khan <shuah@kernel.org> <shuahkhan@gmail.com>
		Shuah Khan <shuah@kernel.org> <shuah.khan@hp.com>
		Shuah Khan <shuah@kernel.org> <shuahkh@osg.samsung.com>
		Shuah Khan <shuah@kernel.org> <shuah.kh@samsung.com>
		Simon Arlott <simon@octiron.net> <simon@fire.lp0.eu>
		Simon Kelley <simon@thekelleys.org.uk>
		Stéphane Witzmann <stephane.witzmann@ubpmes.univ-bpclermont.fr>
		Stephen Hemminger <shemminger@osdl.org>

Documentation/devicetree/bindings/arm/rockchip.yaml

+2 −2

Original line number	Diff line number	Diff line
		@@ -496,12 +496,12 @@ properties:

		- description: Theobroma Systems RK3368-uQ7 with Haikou baseboard
		items:
		- const: tsd,rk3368-uq7-haikou
		- const: tsd,rk3368-lion-haikou
		- const: rockchip,rk3368

		- description: Theobroma Systems RK3399-Q7 with Haikou baseboard
		items:
		- const: tsd,rk3399-q7-haikou
		- const: tsd,rk3399-puma-haikou
		- const: rockchip,rk3399

		- description: Tronsmart Orion R68 Meta

Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml

+3 −6

Original line number	Diff line number	Diff line
		# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/arm/allwinner,sun4i-a10-csi.yaml#
		$id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-csi.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Allwinner A10 CMOS Sensor Interface (CSI) Device Tree Bindings
		@@ -27,14 +27,12 @@ properties:
		clocks:
		items:
		- description: The CSI interface clock
		- description: The CSI module clock
		- description: The CSI ISP clock
		- description: The CSI DRAM clock

		clock-names:
		items:
		- const: bus
		- const: mod
		- const: isp
		- const: ram

		@@ -89,9 +87,8 @@ examples:
		compatible = "allwinner,sun7i-a20-csi0";
		reg = <0x01c09000 0x1000>;
		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI0>,
		<&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
		clock-names = "bus", "mod", "isp", "ram";
		clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
		clock-names = "bus", "isp", "ram";
		resets = <&ccu RST_CSI0>;

		port {

Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml

+42 −44

Original line number	Diff line number	Diff line
		@@ -33,13 +33,13 @@ patternProperties:
		allOf:
		- $ref: "/schemas/types.yaml#/definitions/string"
		- enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
		ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, ESPI,
		ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1,
		GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2,
		GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12,
		I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7,
		I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, LPC,
		LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2,
		ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC,
		ESPI, ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWSPIWP, GPIT0,
		GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
		GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, I2C1, I2C10, I2C11,
		I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6,
		I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ,
		LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2,
		MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2,
		NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3,
		NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1,
		@@ -48,47 +48,45 @@ patternProperties:
		PWM8, PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3,
		RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12,
		SALT13, SALT14, SALT15, SALT16, SALT2, SALT3, SALT4, SALT5,
		SALT6, SALT7, SALT8, SALT9, SD1, SD2, SD3, SD3DAT4, SD3DAT5,
		SD3DAT6, SD3DAT7, SGPM1, SGPS1, SIOONCTRL, SIOPBI, SIOPBO,
		SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1,
		SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11,
		TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5,
		TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1,
		TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13, UART6, UART7,
		UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3,
		WDTRST4, ]
		SALT6, SALT7, SALT8, SALT9, SD1, SD2, SGPM1, SGPS1, SIOONCTRL,
		SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1,
		SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1,
		TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3,
		TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2,
		THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13,
		UART6, UART7, UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2,
		WDTRST3, WDTRST4, ]
		groups:
		allOf:
		- $ref: "/schemas/types.yaml#/definitions/string"
		- enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
		ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, ESPI,
		ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWQSPID, FWSPIWP, GPIT0,
		GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
		GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1,
		I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3,
		I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6,
		JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ,
		MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3,
		MDIO4, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4,
		NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1,
		NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE,
		PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, PWM12G0, PWM12G1,
		PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, PWM15G1, PWM2, PWM3,
		PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, PWM9G0, PWM9G1, QSPI1,
		QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3,
		RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1,
		SALT11G0, SALT11G1, SALT12G0, SALT12G1, SALT13G0, SALT13G1,
		SALT14G0, SALT14G1, SALT15G0, SALT15G1, SALT16G0, SALT16G1,
		SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9G0,
		SALT9G1, SD1, SD2, SD3, SD3DAT4, SD3DAT5, SD3DAT6, SD3DAT7,
		SGPM1, SGPS1, SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD,
		SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2,
		SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13,
		TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8,
		TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4,
		UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6,
		UART7, UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3,
		WDTRST4, ]
		ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1,
		EMMCG4, EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID,
		FWQSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5,
		GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5, GPIU6,
		GPIU7, HVI3C3, HVI3C4, I2C1, I2C10, I2C11, I2C12, I2C13, I2C14,
		I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9,
		I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD,
		LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3, MACLINK4,
		MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1,
		NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2,
		NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4,
		OSCCLK, PEWAKE, PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1,
		PWM12G0, PWM12G1, PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0,
		PWM15G1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1,
		PWM9G0, PWM9G1, QSPI1, QSPI2, RGMII1, RGMII2, RGMII3, RGMII4,
		RMII1, RMII2, RMII3, RMII4, RXD1, RXD2, RXD3, RXD4, SALT1,
		SALT10G0, SALT10G1, SALT11G0, SALT11G1, SALT12G0, SALT12G1,
		SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0, SALT15G1,
		SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7,
		SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPS1, SIOONCTRL,
		SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1,
		SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1,
		TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3,
		TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2,
		THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12G0,
		UART12G1, UART13G0, UART13G1, UART6, UART7, UART8, UART9, VB,
		VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4, ]

		required:
		- compatible

Documentation/devicetree/bindings/regulator/fixed-regulator.yaml

+2 −2

Original line number	Diff line number	Diff line
		@@ -30,8 +30,8 @@ if:
		properties:
		compatible:
		enum:
		- const: regulator-fixed
		- const: regulator-fixed-clock
		- regulator-fixed
		- regulator-fixed-clock

		regulator-name: true

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