Merge branch 'brcm-pseudo-phy-addr' (1531407c) · Commits · 戴 / test

drivers/net/dsa/bcm_sf2.c

+4 −3

Original line number	Original line	Diff line number	Diff line
	@@ -24,6 +24,7 @@
	#include <net/dsa.h>		#include <net/dsa.h>
	#include <linux/ethtool.h>		#include <linux/ethtool.h>
	#include <linux/if_bridge.h>		#include <linux/if_bridge.h>
			#include <linux/brcmphy.h>

	#include "bcm_sf2.h"		#include "bcm_sf2.h"
	#include "bcm_sf2_regs.h"		#include "bcm_sf2_regs.h"
	@@ -697,7 +698,7 @@ static int bcm_sf2_sw_setup(struct dsa_switch *ds)
	/* Include the pseudo-PHY address and the broadcast PHY address to		/* Include the pseudo-PHY address and the broadcast PHY address to
	* divert reads towards our workaround		* divert reads towards our workaround
	*/		*/
	ds->phys_mii_mask \|= ((1 << 30) \| (1 << 0));		ds->phys_mii_mask \|= ((1 << BRCM_PSEUDO_PHY_ADDR) \| (1 << 0));

	rev = reg_readl(priv, REG_SWITCH_REVISION);		rev = reg_readl(priv, REG_SWITCH_REVISION);
	priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &		priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
	@@ -782,7 +783,7 @@ static int bcm_sf2_sw_phy_read(struct dsa_switch *ds, int addr, int regnum)
	*/		*/
	switch (addr) {		switch (addr) {
	case 0:		case 0:
	case 30:		case BRCM_PSEUDO_PHY_ADDR:
	return bcm_sf2_sw_indir_rw(ds, 1, addr, regnum, 0);		return bcm_sf2_sw_indir_rw(ds, 1, addr, regnum, 0);
	default:		default:
	return 0xffff;		return 0xffff;
	@@ -797,7 +798,7 @@ static int bcm_sf2_sw_phy_write(struct dsa_switch *ds, int addr, int regnum,
	*/		*/
	switch (addr) {		switch (addr) {
	case 0:		case 0:
	case 30:		case BRCM_PSEUDO_PHY_ADDR:
	bcm_sf2_sw_indir_rw(ds, 0, addr, regnum, val);		bcm_sf2_sw_indir_rw(ds, 0, addr, regnum, val);
	break;		break;
	}		}

drivers/net/ethernet/broadcom/b44.h

+6 −2

Original line number	Original line	Diff line number	Diff line
	#ifndef _B44_H		#ifndef _B44_H
	#define _B44_H		#define _B44_H

			#include <linux/brcmphy.h>

	/* Register layout. (These correspond to struct _bcmenettregs in bcm4400.) */		/* Register layout. (These correspond to struct _bcmenettregs in bcm4400.) */
	#define B44_DEVCTRL 0x0000UL /* Device Control */		#define B44_DEVCTRL 0x0000UL /* Device Control */
	#define DEVCTRL_MPM 0x00000040 /* Magic Packet PME Enable (B0 only) */		#define DEVCTRL_MPM 0x00000040 /* Magic Packet PME Enable (B0 only) */
	@@ -281,8 +283,10 @@ struct ring_info {
	};		};

	#define B44_MCAST_TABLE_SIZE 32		#define B44_MCAST_TABLE_SIZE 32
	#define B44_PHY_ADDR_NO_LOCAL_PHY 30 /* no local phy regs */		/* no local phy regs, e.g: Broadcom switches pseudo-PHY */
	#define B44_PHY_ADDR_NO_PHY 31 /* no phy present at all */		#define B44_PHY_ADDR_NO_LOCAL_PHY BRCM_PSEUDO_PHY_ADDR
			/* no phy present at all */
			#define B44_PHY_ADDR_NO_PHY 31
	#define B44_MDC_RATIO 5000000		#define B44_MDC_RATIO 5000000

	#define B44_STAT_REG_DECLARE \		#define B44_STAT_REG_DECLARE \

drivers/net/ethernet/broadcom/bgmac.h

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -13,6 +13,7 @@
	dev_dbg(&(bgmac)->core->dev, fmt, ##__VA_ARGS__)		dev_dbg(&(bgmac)->core->dev, fmt, ##__VA_ARGS__)

	#include <linux/bcma/bcma.h>		#include <linux/bcma/bcma.h>
			#include <linux/brcmphy.h>
	#include <linux/netdevice.h>		#include <linux/netdevice.h>

	#define BGMAC_DEV_CTL 0x000		#define BGMAC_DEV_CTL 0x000
	@@ -349,7 +350,7 @@
	#define BGMAC_DESC_CTL0_SOF 0x80000000 /* Start of frame */		#define BGMAC_DESC_CTL0_SOF 0x80000000 /* Start of frame */
	#define BGMAC_DESC_CTL1_LEN 0x00001FFF		#define BGMAC_DESC_CTL1_LEN 0x00001FFF

	#define BGMAC_PHY_NOREGS 0x1E		#define BGMAC_PHY_NOREGS BRCM_PSEUDO_PHY_ADDR
	#define BGMAC_PHY_MASK 0x1F		#define BGMAC_PHY_MASK 0x1F

	#define BGMAC_MAX_TX_RINGS 4		#define BGMAC_MAX_TX_RINGS 4

include/linux/brcmphy.h

+7 −0

Original line number	Original line	Diff line number	Diff line
	#ifndef _LINUX_BRCMPHY_H		#ifndef _LINUX_BRCMPHY_H
	#define _LINUX_BRCMPHY_H		#define _LINUX_BRCMPHY_H

			#include <linux/phy.h>

			/* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used
			* to configure the switch internal registers via MDIO accesses.
			*/
			#define BRCM_PSEUDO_PHY_ADDR 30

	#define PHY_ID_BCM50610 0x0143bd60		#define PHY_ID_BCM50610 0x0143bd60
	#define PHY_ID_BCM50610M 0x0143bd70		#define PHY_ID_BCM50610M 0x0143bd70
	#define PHY_ID_BCM5241 0x0143bc30		#define PHY_ID_BCM5241 0x0143bc30

Admin message