Commit 1527eda3 authored Aug 19, 2016 by Robin Murphy Committed by Russell King Aug 23, 2016

ARM: 8600/1: Enforce some NS-SVC initialisation



Since the non-secure copies of banked registers lack architecturally
defined reset values, there is no actual guarantee when entering in Hyp
from secure-only firmware that the Non-Secure PL1 state will look the
way that kernel entry (in particular the decompressor stub) expects.
So far, we've been getting away with it thanks to implementation details
of ARMv7 cores and/or bootloader behaviour, but for the sake of forwards
compatibility let's try to ensure that we have a minimally sane state
before dropping down into it.

Cc: Russell King <linux@armlinux.org.uk>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

parent f271b779

arch/arm/kernel/hyp-stub.S

+13 −0

Original line number	Original line	Diff line number	Diff line
	@@ -142,6 +142,19 @@ ARM_BE8(orr r7, r7, #(1 << 25)) @ HSCTLR.EE
	and r7, #0x1f @ Preserve HPMN		and r7, #0x1f @ Preserve HPMN
	mcr p15, 4, r7, c1, c1, 1 @ HDCR		mcr p15, 4, r7, c1, c1, 1 @ HDCR

			@ Make sure NS-SVC is initialised appropriately
			mrc p15, 0, r7, c1, c0, 0 @ SCTLR
			orr r7, #(1 << 5) @ CP15 barriers enabled
			bic r7, #(3 << 7) @ Clear SED/ITD for v8 (RES0 for v7)
			bic r7, #(3 << 19) @ WXN and UWXN disabled
			mcr p15, 0, r7, c1, c0, 0 @ SCTLR

			mrc p15, 0, r7, c0, c0, 0 @ MIDR
			mcr p15, 4, r7, c0, c0, 0 @ VPIDR

			mrc p15, 0, r7, c0, c0, 5 @ MPIDR
			mcr p15, 4, r7, c0, c0, 5 @ VMPIDR

	#if !defined(ZIMAGE) && defined(CONFIG_ARM_ARCH_TIMER)		#if !defined(ZIMAGE) && defined(CONFIG_ARM_ARCH_TIMER)
	@ make CNTP_* and CNTPCT accessible from PL1		@ make CNTP_* and CNTPCT accessible from PL1
	mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1		mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1

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