Commit 14f49be4 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915: Add Wa_1406306137:icl,ehl 



v2:
 - Move to context workarounds.  ROW_CHICKEN4 is part of the context
   image on gen11 (although it isn't on gen12).

Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200311162300.1838847-5-matthew.d.roper@intel.com


Reviewed-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
parent d0ed510a

drivers/gpu/drm/i915/gt/intel_workarounds.c

+3 −0
Original line number Diff line number Diff line
@@ -581,6 +581,9 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, 
	wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER,

			   0, /* write-only register; skip validation */

			   0xFFFFFFFF);



	/* Wa_1406306137:icl,ehl */

	wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);

}



static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -9151,6 +9151,7 @@ enum { 


#define GEN9_ROW_CHICKEN4		_MMIO(0xe48c)

#define   GEN12_DISABLE_TDL_PUSH	REG_BIT(9)

#define   GEN11_DIS_PICK_2ND_EU		REG_BIT(7)



#define HSW_ROW_CHICKEN3		_MMIO(0xe49c)

#define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)

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