Commit 14f3a5cc authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'phy-for-5.8' of... 

Merge tag 'phy-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

 into usb-next

Kishon writes:

phy: for 5.8

*) Add new PHY driver to support Cadence SALVO PHY which supports USB3 & USB2
*) Add new PHY driver to support Intel ComboPhy which supports PCIe, SATA and
   EMAC
*) Add new PHY driver for Qualcomm IPQ40xx USB PHY
*) Add new PHY driver for Synopsys FemtoPHY V2 driver used in Qualcomm SOCs
*) Add support for Qualcomm SM8250 UFS PHY and SM8150 QMP USB3 PHY in
   qcom-qmp-phy driver
*) Add support for Amlogic USB2 PHY on Meson8m2 in phy-meson8b-usb2 driver
*) Add DisplayPort mode support in Wiz (TI Cadence PHY wrapper), to enable eDP
   in TI's J721E SoC
*) Add support for super speed USB PHY in TI's AM654 SoC
*) Add fix in Broadcom Stingray USB PHY to get USB PHY PLL lock reliably
*) Add fix in Samsung phy-s5pv210-usb2 to get USB working on s5pv210
*) Add fix in Amlogic phy-meson8b-usb2 to get host only mode working on Meson8
*) Add fix in Cadence phy-cadence-sierra to get USB3 device disconnect issue
*) Convert meson8b-usb2-phy, qcom-qmp-phy, rcar-gen3-phy-usb2 and
   rcar-gen3-phy-usb3 device tree binding to YAML schema
*) Minor fixes and cleanups in phy-cpcap-usb, j721e-wiz, omap-usb2,
   phy-bcm-sr-usb, phy-brcm-usb PHY driver

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>

* tag 'phy-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (43 commits)
  phy: intel: Add driver support for ComboPhy
  dt-bindings: phy: Add YAML schemas for Intel ComboPhy
  dt-bindings: phy: Add PHY_TYPE_XPCS definition
  phy: qcom-qmp: Add QMP V3 USB3 PHY support for SC7180
  dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SC7180
  dt-bindings: phy: qcom,qmp-usb3-dp: Add dt bindings for USB3 DP PHY
  dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml
  phy: cadence: sierra: Fix for USB3 U1/U2 state
  phy: ti: am654: add support for USB super-speed
  phy: ti: am654: show up in regmap debugfs
  drivers: phy: sr-usb: do not use internal fsm for USB2 phy init
  dt-bindings: phy: renesas: usb3-phy: add r8a77961 support
  dt-bindings: phy: renesas: usb3-phy: convert bindings to json-schema
  dt-bindings: phy: renesas: usb2-phy: add r8a77961 support
  dt-bindings: phy: renesas: usb2-phy: convert bindings to json-schema
  phy: qcom-qmp: Ensure register indirection arrays initialized
  phy: omap-usb2: Clean up exported header
  phy: phy-bcm-ns2-usbdrd: Constify phy_ops
  phy: phy-brcm-usb: Constify static structs
  phy: sr-usb: Constify phy_ops
  ...
parents e9ccc35b ac0a95a3

Documentation/devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/phy/amlogic,meson8b-usb2-phy.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Amlogic Meson8, Meson8b, Meson8m2 and GXBB USB2 PHY



maintainers:

  - Martin Blumenstingl <martin.blumenstingl@googlemail.com>



properties:

  compatible:

    oneOf:

      - items:

          - enum:

              - amlogic,meson8-usb2-phy

              - amlogic,meson8b-usb2-phy

              - amlogic,meson8m2-usb2-phy

          - const: amlogic,meson-mx-usb2-phy

      - const: amlogic,meson-gxbb-usb2-phy



  reg:

    maxItems: 1



  clocks:

    minItems: 2



  clock-names:

    items:

      - const: usb_general

      - const: usb



  resets:

    minItems: 1



  "#phy-cells":

    const: 0



  phy-supply:

    description:

      Phandle to a regulator that provides power to the PHY. This

      regulator will be managed during the PHY power on/off sequence.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - "#phy-cells"



additionalProperties: false



examples:

  - |

    usb-phy@c0000000 {

      compatible = "amlogic,meson-gxbb-usb2-phy";

      reg = <0xc0000000 0x20>;

      resets = <&reset_usb_phy>;

      clocks = <&clk_usb_general>, <&reset_usb>;

      clock-names = "usb_general", "usb";

      phy-supply = <&usb_vbus>;

      #phy-cells = <0>;

    };

Documentation/devicetree/bindings/phy/cdns,salvo-phy.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# Copyright (c) 2020 NXP

%YAML 1.2

---

$id: "http://devicetree.org/schemas/phy/cdns,salvo-phy.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Cadence SALVO PHY



maintainers:

  - Peter Chen <peter.chen@nxp.com>



properties:

  compatible:

    enum:

      - nxp,salvo-phy



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    items:

      - const: salvo_phy_clk



  power-domains:

    maxItems: 1



  "#phy-cells":

    const: 0



required:

  - compatible

  - reg

  - "#phy-cells"



additionalProperties: false



examples:

  - |

    #include <dt-bindings/firmware/imx/rsrc.h>



    usb3phy: usb3-phy@5b160000 {

        compatible = "nxp,salvo-phy";

        reg = <0x5b160000 0x40000>;

        clocks = <&usb3_lpcg 4>;

        clock-names = "salvo_phy_clk";

        power-domains = <&pd IMX_SC_R_USB_2_PHY>;

        #phy-cells = <0>;

    };

Documentation/devicetree/bindings/phy/intel,combo-phy.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Intel ComboPhy Subsystem



maintainers:

  - Dilip Kota <eswara.kota@linux.intel.com>



description: |

  Intel Combophy subsystem supports PHYs for PCIe, EMAC and SATA

  controllers. A single Combophy provides two PHY instances.



properties:

  $nodename:

    pattern: "combophy(@.*|-[0-9a-f])*$"



  compatible:

    items:

      - const: intel,combophy-lgm

      - const: intel,combo-phy



  clocks:

    maxItems: 1



  reg:

    items:

      - description: ComboPhy core registers

      - description: PCIe app core control registers



  reg-names:

    items:

      - const: core

      - const: app



  resets:

    maxItems: 4



  reset-names:

    items:

      - const: phy

      - const: core

      - const: iphy0

      - const: iphy1



  intel,syscfg:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    description: Chip configuration registers handle and ComboPhy instance id



  intel,hsio:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    description: HSIO registers handle and ComboPhy instance id on NOC



  intel,aggregation:

    type: boolean

    description: |

      Specify the flag to configure ComboPHY in dual lane mode.



  intel,phy-mode:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Mode of the two phys in ComboPhy.

      See dt-bindings/phy/phy.h for values.



  "#phy-cells":

    const: 1



required:

  - compatible

  - clocks

  - reg

  - reg-names

  - intel,syscfg

  - intel,hsio

  - intel,phy-mode

  - "#phy-cells"



additionalProperties: false



examples:

  - |

    #include <dt-bindings/phy/phy.h>

    combophy@d0a00000 {

        compatible = "intel,combophy-lgm", "intel,combo-phy";

        clocks = <&cgu0 1>;

        #phy-cells = <1>;

        reg = <0xd0a00000 0x40000>,

              <0xd0a40000 0x1000>;

        reg-names = "core", "app";

        resets = <&rcu0 0x50 6>,

                 <&rcu0 0x50 17>,

                 <&rcu0 0x50 23>,

                 <&rcu0 0x50 24>;

        reset-names = "phy", "core", "iphy0", "iphy1";

        intel,syscfg = <&sysconf 0>;

        intel,hsio = <&hsiol 0>;

        intel,phy-mode = <PHY_TYPE_PCIE>;

        intel,aggregation;

    };

Documentation/devicetree/bindings/phy/meson8b-usb2-phy.txt

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* Amlogic Meson8, Meson8b and GXBB USB2 PHY



Required properties:

- compatible:	Depending on the platform this should be one of:

	"amlogic,meson8-usb2-phy"

	"amlogic,meson8b-usb2-phy"

	"amlogic,meson-gxbb-usb2-phy"

- reg:		The base address and length of the registers

- #phys-cells:	should be 0 (see phy-bindings.txt in this directory)

- clocks:	phandle and clock identifier for the phy clocks

- clock-names:	"usb_general" and "usb"



Optional properties:

- resets:	reference to the reset controller

- phy-supply:	see phy-bindings.txt in this directory





Example:



usb0_phy: usb-phy@c0000000 {

	compatible = "amlogic,meson-gxbb-usb2-phy";

	#phy-cells = <0>;

	reg = <0x0 0xc0000000 0x0 0x20>;

	resets = <&reset RESET_USB_OTG>;

	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;

	clock-names = "usb_general", "usb";

	phy-supply = <&usb_vbus>;

};

Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)



%YAML 1.2

---

$id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Qualcomm QMP PHY controller



maintainers:

  - Manu Gautam <mgautam@codeaurora.org>



description:

  QMP phy controller supports physical layer functionality for a number of

  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.



properties:

  compatible:

    enum:

      - qcom,ipq8074-qmp-pcie-phy

      - qcom,msm8996-qmp-pcie-phy

      - qcom,msm8996-qmp-ufs-phy

      - qcom,msm8996-qmp-usb3-phy

      - qcom,msm8998-qmp-pcie-phy

      - qcom,msm8998-qmp-ufs-phy

      - qcom,msm8998-qmp-usb3-phy

      - qcom,sdm845-qhp-pcie-phy

      - qcom,sdm845-qmp-pcie-phy

      - qcom,sdm845-qmp-ufs-phy

      - qcom,sdm845-qmp-usb3-uni-phy

      - qcom,sm8150-qmp-ufs-phy

      - qcom,sm8250-qmp-ufs-phy



  reg:

    items:

      - description: Address and length of PHY's common serdes block.



  "#clock-cells":

     enum: [ 1, 2 ]



  "#address-cells":

    enum: [ 1, 2 ]



  "#size-cells":

    enum: [ 1, 2 ]



  clocks:

    minItems: 1

    maxItems: 4



  clock-names:

    minItems: 1

    maxItems: 4



  resets:

    minItems: 1

    maxItems: 3



  reset-names:

    minItems: 1

    maxItems: 3



  vdda-phy-supply:

    description:

        Phandle to a regulator supply to PHY core block.



  vdda-pll-supply:

    description:

        Phandle to 1.8V regulator supply to PHY refclk pll block.



  vddp-ref-clk-supply:

    description:

        Phandle to a regulator supply to any specific refclk

        pll block.



#Required nodes:

patternProperties:

  "^phy@[0-9a-f]+$":

    type: object

    description:

      Each device node of QMP phy is required to have as many child nodes as

      the number of lanes the PHY has.



required:

  - compatible

  - reg

  - "#clock-cells"

  - "#address-cells"

  - "#size-cells"

  - clocks

  - clock-names

  - resets

  - reset-names

  - vdda-phy-supply

  - vdda-pll-supply



additionalProperties: false



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,sdm845-qmp-usb3-uni-phy

    then:

      properties:

        clocks:

          items:

            - description: Phy aux clock.

            - description: Phy config clock.

            - description: 19.2 MHz ref clk.

            - description: Phy common block aux clock.

        clock-names:

          items:

            - const: aux

            - const: cfg_ahb

            - const: ref

            - const: com_aux

        resets:

          items:

            - description: reset of phy block.

            - description: phy common block reset.

        reset-names:

          items:

            - const: phy

            - const: common

  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,msm8996-qmp-pcie-phy

    then:

      properties:

        clocks:

          items:

            - description: Phy aux clock.

            - description: Phy config clock.

            - description: 19.2 MHz ref clk.

        clock-names:

          items:

            - const: aux

            - const: cfg_ahb

            - const: ref

        resets:

          items:

            - description: reset of phy block.

            - description: phy common block reset.

            - description: phy's ahb cfg block reset.

        reset-names:

          items:

            - const: phy

            - const: common

            - const: cfg

  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,msm8996-qmp-usb3-phy

              - qcom,msm8998-qmp-pcie-phy

              - qcom,msm8998-qmp-usb3-phy

    then:

      properties:

        clocks:

          items:

            - description: Phy aux clock.

            - description: Phy config clock.

            - description: 19.2 MHz ref clk.

        clock-names:

          items:

            - const: aux

            - const: cfg_ahb

            - const: ref

        resets:

          items:

            - description: reset of phy block.

            - description: phy common block reset.

        reset-names:

          items:

             - const: phy

             - const: common

  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,msm8996-qmp-ufs-phy

    then:

      properties:

        clocks:

          items:

            - description: 19.2 MHz ref clk.

        clock-names:

          items:

            - const: ref

        resets:

          items:

            - description: PHY reset in the UFS controller.

        reset-names:

          items:

            - const: ufsphy

  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,msm8998-qmp-ufs-phy

              - qcom,sdm845-qmp-ufs-phy

              - qcom,sm8150-qmp-ufs-phy

              - qcom,sm8250-qmp-ufs-phy

    then:

      properties:

        clocks:

          items:

            - description: 19.2 MHz ref clk.

            - description: Phy reference aux clock.

        clock-names:

          items:

            - const: ref

            - const: ref_aux

        resets:

          items:

            - description: PHY reset in the UFS controller.

        reset-names:

          items:

            - const: ufsphy

  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,ipq8074-qmp-pcie-phy

    then:

      properties:

        clocks:

          items:

            - description: pipe clk.

        clock-names:

          items:

            - const: pipe_clk

        resets:

          items:

            - description: reset of phy block.

            - description: phy common block reset.

        reset-names:

          items:

            - const: phy

            - const: common

  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,sdm845-qhp-pcie-phy

              - qcom,sdm845-qmp-pcie-phy

    then:

      properties:

        clocks:

          items:

            - description: Phy aux clock.

            - description: Phy config clock.

            - description: 19.2 MHz ref clk.

            - description: Phy refgen clk.

        clock-names:

          items:

            - const: aux

            - const: cfg_ahb

            - const: ref

            - const: refgen

        resets:

          items:

            - description: reset of phy block.

        reset-names:

          items:

            - const: phy



examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-sdm845.h>

    usb_2_qmpphy: phy-wrapper@88eb000 {

        compatible = "qcom,sdm845-qmp-usb3-uni-phy";

        reg = <0 0x088eb000 0 0x18c>;

        #clock-cells = <1>;

        #address-cells = <2>;

        #size-cells = <2>;



        clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >,

                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,

                 <&gcc GCC_USB3_SEC_CLKREF_CLK>,

                 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;

        clock-names = "aux", "cfg_ahb", "ref", "com_aux";



        resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,

                 <&gcc GCC_USB3_PHY_SEC_BCR>;

        reset-names = "phy", "common";



        vdda-phy-supply = <&vdda_usb2_ss_1p2>;

        vdda-pll-supply = <&vdda_usb2_ss_core>;



        usb_2_ssphy: phy@88eb200 {

                reg = <0 0x088eb200 0 0x128>,

                      <0 0x088eb400 0 0x1fc>,

                      <0 0x088eb800 0 0x218>,

                      <0 0x088eb600 0 0x70>;

                #clock-cells = <0>;

                #phy-cells = <0>;

                clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;

                clock-names = "pipe0";

                clock-output-names = "usb3_uni_phy_pipe_clk_src";

            };

        };

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