Commit 14ed9cc7 authored by Wayne Boyer's avatar Wayne Boyer Committed by James Bottomley
Browse files

[SCSI] ipr: Add support to flash FPGA and flash back DRAM images 



The write buffer command is used to download and burn new IOA FW images.
The same interface can now be used to flash FPGA and flash back DRAM images.
To download and flash the new images takes more than 15 minutes, so increase
the write buffer command timeout to 30 minutes.

The FPGA and flash back DRAM images don't have the same card_type as the IOA FW
image. So, remove the sanity checking from the driver.  The adapter has sanity
checking and will only accept a valid image.

Signed-off-by: default avatarWayne Boyer <wayneb@linux.vnet.ibm.com>
Acked-by: default avatarBrian King <brking@linux.vnet.ibm.com>
Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
parent 1a34c064

drivers/scsi/ipr.c

+2 −8
Original line number Diff line number Diff line
@@ -3751,14 +3751,6 @@ static ssize_t ipr_store_update_fw(struct device *dev, 


	image_hdr = (struct ipr_ucode_image_header *)fw_entry->data;



	if (be32_to_cpu(image_hdr->header_length) > fw_entry->size ||

	    (ioa_cfg->vpd_cbs->page3_data.card_type &&

	     ioa_cfg->vpd_cbs->page3_data.card_type != image_hdr->card_type)) {

		dev_err(&ioa_cfg->pdev->dev, "Invalid microcode buffer\n");

		release_firmware(fw_entry);

		return -EINVAL;

	}



	src = (u8 *)image_hdr + be32_to_cpu(image_hdr->header_length);

	dnld_size = fw_entry->size - be32_to_cpu(image_hdr->header_length);

	sglist = ipr_alloc_ucode_buffer(dnld_size);
@@ -3777,6 +3769,8 @@ static ssize_t ipr_store_update_fw(struct device *dev, 
		goto out;

	}



	ipr_info("Updating microcode, please be patient.  This may take up to 30 minutes.\n");



	result = ipr_update_ioa_ucode(ioa_cfg, sglist);



	if (!result)

drivers/scsi/ipr.h

+1 −1
Original line number Diff line number Diff line
@@ -208,7 +208,7 @@ 
#define IPR_CANCEL_ALL_TIMEOUT		(ipr_fastfail ? 10 * HZ : 30 * HZ)

#define IPR_ABORT_TASK_TIMEOUT		(ipr_fastfail ? 10 * HZ : 30 * HZ)

#define IPR_INTERNAL_TIMEOUT			(ipr_fastfail ? 10 * HZ : 30 * HZ)

#define IPR_WRITE_BUFFER_TIMEOUT		(10 * 60 * HZ)

#define IPR_WRITE_BUFFER_TIMEOUT		(30 * 60 * HZ)

#define IPR_SET_SUP_DEVICE_TIMEOUT		(2 * 60 * HZ)

#define IPR_REQUEST_SENSE_TIMEOUT		(10 * HZ)

#define IPR_OPERATIONAL_TIMEOUT		(5 * 60)

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