clk/exynos5420: fix the order of parents of hdmi mux (14d87cda) · Commits · 戴 / test

Listing sclk_hdmiphy at 0th position in the list of parents is causing wrong configuration in reg SRC_DISP10. Signed-off-by:

drivers/clk/samsung/clk-exynos5420.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -286,7 +286,7 @@ PNAME(audio2_p) = { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll",
		"sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
		PNAME(spdif_p) = { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2",
		"spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" };
		PNAME(hdmi_p) = { "sclk_hdmiphy", "dout_hdmi_pixel" };
		PNAME(hdmi_p) = { "dout_hdmi_pixel", "sclk_hdmiphy" };
		PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll",
		"sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };