Commit 14cdf8cb authored by Linus Walleij's avatar Linus Walleij
Browse files

ARM: ux500: add some DB8500 DMA channel info 



This adds some missing DMA channel information to the disabled
MMC/SD/SDIO blocks number 3 and 5, and notes that the assignment
of MSP channels vary with ASIC variant.

Reviewed-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 4ada2129

arch/arm/boot/dts/ste-dbx5x0.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -875,6 +875,10 @@ 
			reg = <0x80119000 0x1000>;

			interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;



			dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */

			       <&dma 41 0 0x0>; /* Logical - MemToDev */

			dma-names = "rx", "tx";



			clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;

			clock-names = "sdi", "apb_pclk";
@@ -901,6 +905,10 @@ 
			reg = <0x80008000 0x1000>;

			interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;



			dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */

			       <&dma 43 0 0x0>; /* Logical - MemToDev */

			dma-names = "rx", "tx";



			clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;

			clock-names = "sdi", "apb_pclk";
@@ -929,6 +937,7 @@ 
			interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;

			v-ape-supply = <&db8500_vape_reg>;



			/* This DMA channel only exist on DB8500 v1 */

			dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */

			dma-names = "tx";
@@ -962,6 +971,7 @@ 
			interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;

			v-ape-supply = <&db8500_vape_reg>;



			/* This DMA channel only exist on DB8500 v2 */

			dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */

			dma-names = "rx";

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