Merge tag 'tegra-for-5.1-dt-bindings' of...

          - const: nvidia,tegra124

      - items:

          - enum:

              - nvidia,darcy

              - nvidia,p2371-0000

              - nvidia,p2371-2180

              - nvidia,p2571

              - nvidia,p2894-0050-a08

          - const: nvidia,tegra210

      - items:

          - enum:

oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop

control module that will automatically adjust the VDD_CPU voltage by

communicating with an off-chip PMIC either via an I2C bus or via PWM signals.

Currently only the I2C mode is supported by these bindings.

Required properties:

- compatible : should be "nvidia,tegra124-dfll"

- compatible : should be one of:

  - "nvidia,tegra124-dfll": for Tegra124

  - "nvidia,tegra210-dfll": for Tegra210

- reg : Defines the following set of registers, in the order listed:

        - registers for the DFLL control logic.

        - registers for the I2C output logic.

Optional properties for the control loop parameters:

- nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.

Optional properties for mode selection:

- nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C.

Required properties for I2C mode:

- nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode.

Example:

Required properties for PWM mode:

- nvidia,pwm-period-nanoseconds: period of PWM square wave in nanoseconds.

- nvidia,pwm-tristate-microvolts: Regulator voltage in micro volts when PWM

  control is disabled and the PWM output is tristated. Note that this voltage is

  configured in hardware, typically via a resistor divider.

- nvidia,pwm-min-microvolts: Regulator voltage in micro volts when PWM control

  is enabled and PWM output is low. Hence, this is the minimum output voltage

  that the regulator supports when PWM control is enabled.

- nvidia,pwm-voltage-step-microvolts: Voltage increase in micro volts

  corresponding to a 1/33th increase in duty cycle. Eg the voltage for 2/33th

  duty cycle would be: nvidia,pwm-min-microvolts +

  nvidia,pwm-voltage-step-microvolts * 2.

- pinctrl-0: I/O pad configuration when PWM control is enabled.

- pinctrl-1: I/O pad configuration when PWM control is disabled.

- pinctrl-names: must include the following entries:

  - dvfs_pwm_enable: I/O pad configuration when PWM control is enabled.

  - dvfs_pwm_disable: I/O pad configuration when PWM control is disabled.

Example for I2C:

clock@70110000 {

        compatible = "nvidia,tegra124-dfll";

        nvidia,i2c-fs-rate = <400000>;

};

Example for PWM:

clock@70110000 {

	compatible = "nvidia,tegra124-dfll";

	reg = <0 0x70110000 0 0x100>, /* DFLL control */

	      <0 0x70110000 0 0x100>, /* I2C output control */

	      <0 0x70110100 0 0x100>, /* Integrated I2C controller */

	      <0 0x70110200 0 0x100>; /* Look-up table RAM */

	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,

	         <&tegra_car TEGRA210_CLK_DFLL_REF>,

		 <&tegra_car TEGRA124_CLK_I2C5>;;

	clock-names = "soc", "ref", "i2c";

	resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;

	reset-names = "dvco";

	#clock-cells = <0>;

	clock-output-names = "dfllCPU_out";

	nvidia,sample-rate = <25000>;

	nvidia,droop-ctrl = <0x00000f00>;

	nvidia,force-mode = <1>;

	nvidia,cf = <6>;

	nvidia,ci = <0>;

	nvidia,cg = <2>;

	nvidia,pwm-min-microvolts = <708000>; /* 708mV */

	nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */

	nvidia,pwm-to-pmic;

	nvidia,pwm-tristate-microvolts = <1000000>;

	nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */

	pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";

	pinctrl-0 = <&dvfs_pwm_active_state>;

	pinctrl-1 = <&dvfs_pwm_inactive_state>;

};

/* pinmux nodes added for completeness. Binding doc can be found in:

 * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt

 */

pinmux: pinmux@700008d4 {

	dvfs_pwm_active_state: dvfs_pwm_active {

		dvfs_pwm_pbb1 {

			nvidia,pins = "dvfs_pwm_pbb1";

			nvidia,tristate = <TEGRA_PIN_DISABLE>;

		};

	};

	dvfs_pwm_inactive_state: dvfs_pwm_inactive {

		dvfs_pwm_pbb1 {

			nvidia,pins = "dvfs_pwm_pbb1";

			nvidia,tristate = <TEGRA_PIN_ENABLE>;

		};

	};

};

  See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

  - cpu_g: Clock mux for the fast CPU cluster.

  - cpu_lp: Clock mux for the low-power CPU cluster.

  - pll_x: Fast PLL clocksource.

  - pll_p: Auxiliary PLL used during fast PLL rate changes.

  - dfll: Fast DFLL clocksource that also automatically scales CPU voltage.

- vdd-cpu-supply: Regulator for CPU voltage

Optional properties:

- clock-latency: Specify the possible maximum transition latency for clock,

		reg = <0>;

		clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,

			 <&tegra_car TEGRA124_CLK_CCLK_LP>,

			 <&tegra_car TEGRA124_CLK_PLL_X>,

			 <&tegra_car TEGRA124_CLK_PLL_P>,

			 <&dfll>;

		clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";

		clock-names = "cpu_g", "pll_x", "pll_p", "dfll";

		clock-latency = <300000>;

		vdd-cpu-supply: <&vdd_cpu>;

	};

	<...>

and BPMP.

Required properties:

- name : Should be bpmp

- compatible

    Array of strings

    One of:

NVIDIA Tegra210 Boot and Power Management Processor (BPMP)

The Boot and Power Management Processor (BPMP) is a co-processor found

in Tegra210 SoC. It is designed to handle the early stages of the boot

process as well as to assisting in entering deep low power state

(suspend to ram), and also offloading DRAM memory clock scaling on

some platforms. The binding document defines the resources that would

be used by the BPMP T210 firmware driver, which can create the

interprocessor communication (IPC) between the CPU and BPMP.

Required properties:

- compatible

    Array of strings

    One of:

    - "nvidia,tegra210-bpmp"

- reg: physical base address and length for HW synchornization primitives

       1) base address and length to Tegra 'atomics' hardware

       2) base address and length to Tegra 'semaphore' hardware

- interrupts: specifies the interrupt number for receiving messages ("rx")

              and for triggering messages ("tx")

Optional properties:

- #clock-cells : Should be 1 for platforms where DRAM clock control is

                 offloaded to bpmp.

Example:

bpmp@70016000 {

	compatible = "nvidia,tegra210-bpmp";

	reg = <0x0 0x70016000 0x0 0x2000

	       0x0 0x60001000 0x0 0x1000>;

	interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,

		     <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;

	interrupt-names = "tx", "rx";

};