Commit 148842c9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86-apic-2020-12-14' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 apic updates from Thomas Gleixner:
 "Yet another large set of x86 interrupt management updates:

   - Simplification and distangling of the MSI related functionality

   - Let IO/APIC construct the RTE entries from an MSI message instead
     of having IO/APIC specific code in the interrupt remapping drivers

   - Make the retrieval of the parent interrupt domain (vector or remap
     unit) less hardcoded and use the relevant irqdomain callbacks for
     selection.

   - Allow the handling of more than 255 CPUs without a virtualized
     IOMMU when the hypervisor supports it. This has made been possible
     by the above modifications and also simplifies the existing
     workaround in the HyperV specific virtual IOMMU.

   - Cleanup of the historical timer_works() irq flags related
     inconsistencies"

* tag 'x86-apic-2020-12-14' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (42 commits)
  x86/ioapic: Cleanup the timer_works() irqflags mess
  iommu/hyper-v: Remove I/O-APIC ID check from hyperv_irq_remapping_select()
  iommu/amd: Fix IOMMU interrupt generation in X2APIC mode
  iommu/amd: Don't register interrupt remapping irqdomain when IR is disabled
  iommu/amd: Fix union of bitfields in intcapxt support
  x86/ioapic: Correct the PCI/ISA trigger type selection
  x86/ioapic: Use I/O-APIC ID for finding irqdomain, not index
  x86/hyperv: Enable 15-bit APIC ID if the hypervisor supports it
  x86/kvm: Enable 15-bit extension when KVM_FEATURE_MSI_EXT_DEST_ID detected
  iommu/hyper-v: Disable IRQ pseudo-remapping if 15 bit APIC IDs are available
  x86/apic: Support 15 bits of APIC ID in MSI where available
  x86/ioapic: Handle Extended Destination ID field in RTE
  iommu/vt-d: Simplify intel_irq_remapping_select()
  x86: Kill all traces of irq_remapping_get_irq_domain()
  x86/ioapic: Use irq_find_matching_fwspec() to find remapping irqdomain
  x86/hpet: Use irq_find_matching_fwspec() to find remapping irqdomain
  iommu/hyper-v: Implement select() method on remapping irqdomain
  iommu/vt-d: Implement select() method on remapping irqdomain
  iommu/amd: Implement select() method on remapping irqdomain
  x86/apic: Add select() method on vector irqdomain
  ...
parents eb0ea741 058df195

arch/x86/include/asm/apic.h

+7 −9
Original line number Diff line number Diff line
@@ -259,6 +259,7 @@ static inline u64 native_x2apic_icr_read(void) 


extern int x2apic_mode;

extern int x2apic_phys;

extern void __init x2apic_set_max_apicid(u32 apicid);

extern void __init check_x2apic(void);

extern void x2apic_setup(void);

static inline int x2apic_enabled(void)
@@ -305,11 +306,10 @@ struct apic { 
	void	(*send_IPI_all)(int vector);

	void	(*send_IPI_self)(int vector);



	/* dest_logical is used by the IPI functions */

	u32	dest_logical;

	u32	disable_esr;

	u32	irq_delivery_mode;

	u32	irq_dest_mode;



	enum apic_delivery_modes delivery_mode;

	bool	dest_mode_logical;



	u32	(*calc_dest_apicid)(unsigned int cpu);
@@ -520,12 +520,10 @@ static inline void apic_smt_update(void) { } 
#endif



struct msi_msg;

struct irq_cfg;



#ifdef CONFIG_PCI_MSI

void x86_vector_msi_compose_msg(struct irq_data *data, struct msi_msg *msg);

#else

# define x86_vector_msi_compose_msg NULL

#endif

extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,

				  bool dmar);



extern void ioapic_zap_locks(void);

arch/x86/include/asm/apicdef.h

+7 −9
Original line number Diff line number Diff line
@@ -432,15 +432,13 @@ struct local_apic { 
 #define BAD_APICID 0xFFFFu

#endif



enum ioapic_irq_destination_types {

	dest_Fixed		= 0,

	dest_LowestPrio		= 1,

	dest_SMI		= 2,

	dest__reserved_1	= 3,

	dest_NMI		= 4,

	dest_INIT		= 5,

	dest__reserved_2	= 6,

	dest_ExtINT		= 7

enum apic_delivery_modes {

	APIC_DELIVERY_MODE_FIXED	= 0,

	APIC_DELIVERY_MODE_LOWESTPRIO   = 1,

	APIC_DELIVERY_MODE_SMI		= 2,

	APIC_DELIVERY_MODE_NMI		= 4,

	APIC_DELIVERY_MODE_INIT		= 5,

	APIC_DELIVERY_MODE_EXTINT	= 7,

};



#endif /* _ASM_X86_APICDEF_H */

arch/x86/include/asm/hpet.h

+0 −11
Original line number Diff line number Diff line
@@ -74,17 +74,6 @@ extern void hpet_disable(void); 
extern unsigned int hpet_readl(unsigned int a);

extern void force_hpet_resume(void);



struct irq_data;

struct hpet_channel;

struct irq_domain;



extern void hpet_msi_unmask(struct irq_data *data);

extern void hpet_msi_mask(struct irq_data *data);

extern void hpet_msi_write(struct hpet_channel *hc, struct msi_msg *msg);

extern struct irq_domain *hpet_create_irq_domain(int hpet_id);

extern int hpet_assign_irq(struct irq_domain *domain,

			   struct hpet_channel *hc, int dev_num);



#ifdef CONFIG_HPET_EMULATE_RTC



#include <linux/interrupt.h>

arch/x86/include/asm/hw_irq.h

+6 −8
Original line number Diff line number Diff line
@@ -39,18 +39,16 @@ enum irq_alloc_type { 
	X86_IRQ_ALLOC_TYPE_PCI_MSI,

	X86_IRQ_ALLOC_TYPE_PCI_MSIX,

	X86_IRQ_ALLOC_TYPE_DMAR,

	X86_IRQ_ALLOC_TYPE_AMDVI,

	X86_IRQ_ALLOC_TYPE_UV,

	X86_IRQ_ALLOC_TYPE_IOAPIC_GET_PARENT,

	X86_IRQ_ALLOC_TYPE_HPET_GET_PARENT,

};



struct ioapic_alloc_info {

	int		pin;

	int		node;

	u32				trigger : 1;

	u32				polarity : 1;

	u32		is_level	: 1;

	u32		active_low	: 1;

	u32		valid		: 1;

	struct IO_APIC_route_entry	*entry;

};



struct uv_alloc_info {

arch/x86/include/asm/hyperv-tlfs.h

+7 −0
Original line number Diff line number Diff line
@@ -23,6 +23,13 @@ 
#define HYPERV_CPUID_IMPLEMENT_LIMITS		0x40000005

#define HYPERV_CPUID_NESTED_FEATURES		0x4000000A



#define HYPERV_CPUID_VIRT_STACK_INTERFACE	0x40000081

#define HYPERV_VS_INTERFACE_EAX_SIGNATURE	0x31235356  /* "VS#1" */



#define HYPERV_CPUID_VIRT_STACK_PROPERTIES	0x40000082

/* Support for the extended IOAPIC RTE format */

#define HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE	BIT(2)



#define HYPERV_HYPERVISOR_PRESENT_BIT		0x80000000

#define HYPERV_CPUID_MIN			0x40000005

#define HYPERV_CPUID_MAX			0x4000ffff

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