Commit 1476253c authored Jul 14, 2015 by Andrew Y. Kuksov Committed by Mark Brown Oct 23, 2015

spi: imx: fix ecspi mode setup



Fixed problem with setting spi mode 0 or 1 after setting mode 2 or 3

SPI_MODE_0 and SPI_MODE_1 requires clock low when inactive. SPI_MODE_2
and SPI_MODE_3 requires clk high when inactive.
Currently driver can just set bits in fields SCLK_PHA (SPI Clock/Data
Phase Control), SCLK_POL (SPI Clock Polarity Control),
SCLK_CTL (controls the inactive state of SCLK) ans SS_POL (SPI SS
Polarity Select) of ECSPIx_CONFIGREG register.
This patch allows driver to clear corresponding bits in these fields.

Signed-off-by: Andrew Y. Kuksov <qxovxp@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

parent 6ff33f39

drivers/spi/spi-imx.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -336,13 +336,20 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,

		if (config->mode & SPI_CPHA)
		cfg \|= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
		else
		cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(config->cs);

		if (config->mode & SPI_CPOL) {
		cfg \|= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
		cfg \|= MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
		} else {
		cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
		cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
		}
		if (config->mode & SPI_CS_HIGH)
		cfg \|= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
		else
		cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(config->cs);

		writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
		writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);

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