clk: renesas: r8a779a0: Fix R and OSC clocks (14653942) · Commits · 戴 / test

The R-Car V3U clock driver defines the R and OSC clocks using R-Car Gen3 clock types. However, The R-Car V3U clock driver does not use the R-Car Gen3 clock driver core, hence registering the R and OSC clocks fails: renesas-cpg-mssr e6150000.clock-controller: Failed to register core clock osc: -22 renesas-cpg-mssr e6150000.clock-controller: Failed to register core clock r: -22 Fix this by introducing clock definition macros specific to R-Car V3U. Note that rcar_r8a779a0_cpg_clk_register() already handled the related clock types. Drop the now unneeded include of rcar-gen3-cpg.h. Fixes: ("clk: renesas: cpg-mssr: Add support for R-Car V3U") Signed-off-by:

Geert Uytterhoeven <geert+renesas@glider.be> Tested-by:

Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by:

Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20201109152614.2465483-1-geert+renesas@glider.be

drivers/clk/renesas/r8a779a0-cpg-mssr.c

+10 −3

Original line number	Diff line number	Diff line
		@@ -26,7 +26,6 @@
		#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>

		#include "renesas-cpg-mssr.h"
		#include "rcar-gen3-cpg.h"

		enum rcar_r8a779a0_clk_types {
		CLK_TYPE_R8A779A0_MAIN = CLK_TYPE_CUSTOM,
		@@ -84,6 +83,14 @@ enum clk_ids {
		DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \
		.offset = _offset)

		#define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
		DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL, \
		(_parent0) << 16 \| (_parent1), \
		.div = (_div0) << 16 \| (_div1), .offset = _md)

		#define DEF_OSC(_name, _id, _parent, _div) \
		DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div)

		static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
		/* External Clock Inputs */
		DEF_INPUT("extal", CLK_EXTAL),
		@@ -136,8 +143,8 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
		DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
		DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),

		DEF_GEN3_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8),
		DEF_GEN3_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
		DEF_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8),
		DEF_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
		};

		static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {

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