octeontx2-af: Add support for CGX link management (1463f382) · Commits · 戴 / test

drivers/net/ethernet/marvell/octeontx2/af/cgx.c

+353 −4

Original line number	Diff line number	Diff line
		@@ -24,16 +24,43 @@
		#define DRV_NAME "octeontx2-cgx"
		#define DRV_STRING "Marvell OcteonTX2 CGX/MAC Driver"

		/**
		* struct lmac
		* @wq_cmd_cmplt: waitq to keep the process blocked until cmd completion
		* @cmd_lock: Lock to serialize the command interface
		* @resp: command response
		* @event_cb: callback for linkchange events
		* @cmd_pend: flag set before new command is started
		* flag cleared after command response is received
		* @cgx: parent cgx port
		* @lmac_id: lmac port id
		* @name: lmac port name
		*/
		struct lmac {
		wait_queue_head_t wq_cmd_cmplt;
		struct mutex cmd_lock;
		u64 resp;
		struct cgx_event_cb event_cb;
		bool cmd_pend;
		struct cgx *cgx;
		u8 lmac_id;
		char *name;
		};

		struct cgx {
		void __iomem *reg_base;
		struct pci_dev *pdev;
		u8 cgx_id;
		u8 lmac_count;
		struct lmac *lmac_idmap[MAX_LMAC_PER_CGX];
		struct list_head cgx_list;
		};

		static LIST_HEAD(cgx_list);

		/* CGX PHY management internal APIs */
		static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool en);

		/* Supported devices */
		static const struct pci_device_id cgx_id_table[] = {
		{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_CGX) },
		@@ -42,11 +69,24 @@ static const struct pci_device_id cgx_id_table[] = {

		MODULE_DEVICE_TABLE(pci, cgx_id_table);

		static void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val)
		{
		writeq(val, cgx->reg_base + (lmac << 18) + offset);
		}

		static u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset)
		{
		return readq(cgx->reg_base + (lmac << 18) + offset);
		}

		static inline struct lmac lmac_pdata(u8 lmac_id, struct cgx cgx)
		{
		if (!cgx \|\| lmac_id >= MAX_LMAC_PER_CGX)
		return NULL;

		return cgx->lmac_idmap[lmac_id];
		}

		int cgx_get_cgx_cnt(void)
		{
		struct cgx *cgx_dev;
		@@ -82,18 +122,312 @@ void *cgx_get_pdata(int cgx_id)
		}
		EXPORT_SYMBOL(cgx_get_pdata);

		static void cgx_lmac_init(struct cgx *cgx)
		/* CGX Firmware interface low level support */
		static int cgx_fwi_cmd_send(u64 req, u64 resp, struct lmac lmac)
		{
		struct cgx *cgx = lmac->cgx;
		struct device *dev;
		int err = 0;
		u64 cmd;

		/* Ensure no other command is in progress */
		err = mutex_lock_interruptible(&lmac->cmd_lock);
		if (err)
		return err;

		/* Ensure command register is free */
		cmd = cgx_read(cgx, lmac->lmac_id, CGX_COMMAND_REG);
		if (FIELD_GET(CMDREG_OWN, cmd) != CGX_CMD_OWN_NS) {
		err = -EBUSY;
		goto unlock;
		}

		/* Update ownership in command request */
		req = FIELD_SET(CMDREG_OWN, CGX_CMD_OWN_FIRMWARE, req);

		/* Mark this lmac as pending, before we start */
		lmac->cmd_pend = true;

		/* Start command in hardware */
		cgx_write(cgx, lmac->lmac_id, CGX_COMMAND_REG, req);

		/* Ensure command is completed without errors */
		if (!wait_event_timeout(lmac->wq_cmd_cmplt, !lmac->cmd_pend,
		msecs_to_jiffies(CGX_CMD_TIMEOUT))) {
		dev = &cgx->pdev->dev;
		dev_err(dev, "cgx port %d:%d cmd timeout\n",
		cgx->cgx_id, lmac->lmac_id);
		err = -EIO;
		goto unlock;
		}

		/* we have a valid command response */
		smp_rmb(); /* Ensure the latest updates are visible */
		*resp = lmac->resp;

		unlock:
		mutex_unlock(&lmac->cmd_lock);

		return err;
		}

		static inline int cgx_fwi_cmd_generic(u64 req, u64 *resp,
		struct cgx *cgx, int lmac_id)
		{
		struct lmac *lmac;
		int err;

		lmac = lmac_pdata(lmac_id, cgx);
		if (!lmac)
		return -ENODEV;

		err = cgx_fwi_cmd_send(req, resp, lmac);

		/* Check for valid response */
		if (!err) {
		if (FIELD_GET(EVTREG_STAT, *resp) == CGX_STAT_FAIL)
		return -EIO;
		else
		return 0;
		}

		return err;
		}

		/* Hardware event handlers */
		static inline void cgx_link_change_handler(u64 lstat,
		struct lmac *lmac)
		{
		struct cgx *cgx = lmac->cgx;
		struct cgx_link_event event;
		struct device *dev;

		dev = &cgx->pdev->dev;

		event.lstat.link_up = FIELD_GET(RESP_LINKSTAT_UP, lstat);
		event.lstat.full_duplex = FIELD_GET(RESP_LINKSTAT_FDUPLEX, lstat);
		event.lstat.speed = FIELD_GET(RESP_LINKSTAT_SPEED, lstat);
		event.lstat.err_type = FIELD_GET(RESP_LINKSTAT_ERRTYPE, lstat);

		event.cgx_id = cgx->cgx_id;
		event.lmac_id = lmac->lmac_id;

		if (!lmac->event_cb.notify_link_chg) {
		dev_dbg(dev, "cgx port %d:%d Link change handler null",
		cgx->cgx_id, lmac->lmac_id);
		if (event.lstat.err_type != CGX_ERR_NONE) {
		dev_err(dev, "cgx port %d:%d Link error %d\n",
		cgx->cgx_id, lmac->lmac_id,
		event.lstat.err_type);
		}
		dev_info(dev, "cgx port %d:%d Link status %s, speed %x\n",
		cgx->cgx_id, lmac->lmac_id,
		event.lstat.link_up ? "UP" : "DOWN",
		event.lstat.speed);
		return;
		}

		if (lmac->event_cb.notify_link_chg(&event, lmac->event_cb.data))
		dev_err(dev, "event notification failure\n");
		}

		static inline bool cgx_cmdresp_is_linkevent(u64 event)
		{
		u8 id;

		id = FIELD_GET(EVTREG_ID, event);
		if (id == CGX_CMD_LINK_BRING_UP \|\|
		id == CGX_CMD_LINK_BRING_DOWN)
		return true;
		else
		return false;
		}

		static inline bool cgx_event_is_linkevent(u64 event)
		{
		if (FIELD_GET(EVTREG_ID, event) == CGX_EVT_LINK_CHANGE)
		return true;
		else
		return false;
		}

		static irqreturn_t cgx_fwi_event_handler(int irq, void *data)
		{
		struct lmac *lmac = data;
		struct device *dev;
		struct cgx *cgx;
		u64 event;

		cgx = lmac->cgx;

		event = cgx_read(cgx, lmac->lmac_id, CGX_EVENT_REG);

		if (!FIELD_GET(EVTREG_ACK, event))
		return IRQ_NONE;

		dev = &cgx->pdev->dev;

		switch (FIELD_GET(EVTREG_EVT_TYPE, event)) {
		case CGX_EVT_CMD_RESP:
		/* Copy the response. Since only one command is active at a
		* time, there is no way a response can get overwritten
		*/
		lmac->resp = event;
		/* Ensure response is updated before thread context starts */
		smp_wmb();

		/* There wont be separate events for link change initiated from
		* software; Hence report the command responses as events
		*/
		if (cgx_cmdresp_is_linkevent(event))
		cgx_link_change_handler(event, lmac);

		/* Release thread waiting for completion */
		lmac->cmd_pend = false;
		wake_up_interruptible(&lmac->wq_cmd_cmplt);
		break;
		case CGX_EVT_ASYNC:
		if (cgx_event_is_linkevent(event))
		cgx_link_change_handler(event, lmac);
		break;
		}

		/* Any new event or command response will be posted by firmware
		* only after the current status is acked.
		* Ack the interrupt register as well.
		*/
		cgx_write(lmac->cgx, lmac->lmac_id, CGX_EVENT_REG, 0);
		cgx_write(lmac->cgx, lmac->lmac_id, CGXX_CMRX_INT, FW_CGX_INT);

		return IRQ_HANDLED;
		}

		/* APIs for PHY management using CGX firmware interface */

		/* callback registration for hardware events like link change */
		int cgx_lmac_evh_register(struct cgx_event_cb cb, void cgxd, int lmac_id)
		{
		struct cgx *cgx = cgxd;
		struct lmac *lmac;

		lmac = lmac_pdata(lmac_id, cgx);
		if (!lmac)
		return -ENODEV;

		lmac->event_cb = *cb;

		return 0;
		}
		EXPORT_SYMBOL(cgx_lmac_evh_register);

		static int cgx_fwi_link_change(struct cgx *cgx, int lmac_id, bool enable)
		{
		u64 req = 0;
		u64 resp;

		if (enable)
		req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_UP, req);
		else
		req = FIELD_SET(CMDREG_ID, CGX_CMD_LINK_BRING_DOWN, req);

		return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id);
		}
		EXPORT_SYMBOL(cgx_fwi_link_change);

		static inline int cgx_fwi_read_version(u64 resp, struct cgx cgx)
		{
		u64 req = 0;

		req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_FW_VER, req);
		return cgx_fwi_cmd_generic(req, resp, cgx, 0);
		}

		static int cgx_lmac_verify_fwi_version(struct cgx *cgx)
		{
		struct device *dev = &cgx->pdev->dev;
		int major_ver, minor_ver;
		u64 resp;
		int err;

		if (!cgx->lmac_count)
		return 0;

		err = cgx_fwi_read_version(&resp, cgx);
		if (err)
		return err;

		major_ver = FIELD_GET(RESP_MAJOR_VER, resp);
		minor_ver = FIELD_GET(RESP_MINOR_VER, resp);
		dev_dbg(dev, "Firmware command interface version = %d.%d\n",
		major_ver, minor_ver);
		if (major_ver != CGX_FIRMWARE_MAJOR_VER \|\|
		minor_ver != CGX_FIRMWARE_MINOR_VER)
		return -EIO;
		else
		return 0;
		}

		static int cgx_lmac_init(struct cgx *cgx)
		{
		struct lmac *lmac;
		int i, err;

		cgx->lmac_count = cgx_read(cgx, 0, CGXX_CMRX_RX_LMACS) & 0x7;
		if (cgx->lmac_count > MAX_LMAC_PER_CGX)
		cgx->lmac_count = MAX_LMAC_PER_CGX;

		for (i = 0; i < cgx->lmac_count; i++) {
		lmac = kcalloc(1, sizeof(struct lmac), GFP_KERNEL);
		if (!lmac)
		return -ENOMEM;
		lmac->name = kcalloc(1, sizeof("cgx_fwi_xxx_yyy"), GFP_KERNEL);
		if (!lmac->name)
		return -ENOMEM;
		sprintf(lmac->name, "cgx_fwi_%d_%d", cgx->cgx_id, i);
		lmac->lmac_id = i;
		lmac->cgx = cgx;
		init_waitqueue_head(&lmac->wq_cmd_cmplt);
		mutex_init(&lmac->cmd_lock);
		err = request_irq(pci_irq_vector(cgx->pdev,
		CGX_LMAC_FWI + i * 9),
		cgx_fwi_event_handler, 0, lmac->name, lmac);
		if (err)
		return err;

		/* Enable interrupt */
		cgx_write(cgx, lmac->lmac_id, CGXX_CMRX_INT_ENA_W1S,
		FW_CGX_INT);

		/* Add reference */
		cgx->lmac_idmap[i] = lmac;
		}

		return cgx_lmac_verify_fwi_version(cgx);
		}

		static int cgx_lmac_exit(struct cgx *cgx)
		{
		struct lmac *lmac;
		int i;

		/* Free all lmac related resources */
		for (i = 0; i < cgx->lmac_count; i++) {
		lmac = cgx->lmac_idmap[i];
		if (!lmac)
		continue;
		free_irq(pci_irq_vector(cgx->pdev, CGX_LMAC_FWI + i * 9), lmac);
		kfree(lmac->name);
		kfree(lmac);
		}

		return 0;
		}

		static int cgx_probe(struct pci_dev pdev, const struct pci_device_id id)
		{
		struct device *dev = &pdev->dev;
		struct cgx *cgx;
		int err;
		int err, nvec;

		cgx = devm_kzalloc(dev, sizeof(*cgx), GFP_KERNEL);
		if (!cgx)
		@@ -123,14 +457,27 @@ static int cgx_probe(struct pci_dev pdev, const struct pci_device_id id)
		goto err_release_regions;
		}

		nvec = CGX_NVEC;
		err = pci_alloc_irq_vectors(pdev, nvec, nvec, PCI_IRQ_MSIX);
		if (err < 0 \|\| err != nvec) {
		dev_err(dev, "Request for %d msix vectors failed, err %d\n",
		nvec, err);
		goto err_release_regions;
		}

		list_add(&cgx->cgx_list, &cgx_list);
		cgx->cgx_id = cgx_get_cgx_cnt() - 1;
		cgx_lmac_init(cgx);

		err = cgx_lmac_init(cgx);
		if (err)
		goto err_release_lmac;

		return 0;

		err_release_regions:
		err_release_lmac:
		cgx_lmac_exit(cgx);
		list_del(&cgx->cgx_list);
		err_release_regions:
		pci_release_regions(pdev);
		err_disable_device:
		pci_disable_device(pdev);
		@@ -142,7 +489,9 @@ static void cgx_remove(struct pci_dev *pdev)
		{
		struct cgx *cgx = pci_get_drvdata(pdev);

		cgx_lmac_exit(cgx);
		list_del(&cgx->cgx_list);
		pci_free_irq_vectors(pdev);
		pci_release_regions(pdev);
		pci_disable_device(pdev);
		pci_set_drvdata(pdev, NULL);

drivers/net/ethernet/marvell/octeontx2/af/cgx.h

+32 −0

Original line number	Diff line number	Diff line
		@@ -11,6 +11,8 @@
		#ifndef CGX_H
		#define CGX_H

		#include "cgx_fw_if.h"

		/* PCI device IDs */
		#define PCI_DEVID_OCTEONTX2_CGX 0xA059

		@@ -22,12 +24,42 @@
		#define CGX_OFFSET(x) ((x) * MAX_LMAC_PER_CGX)

		/* Registers */
		#define CGXX_CMRX_INT 0x040
		#define FW_CGX_INT BIT_ULL(1)
		#define CGXX_CMRX_INT_ENA_W1S 0x058
		#define CGXX_CMRX_RX_ID_MAP 0x060
		#define CGXX_CMRX_RX_LMACS 0x128
		#define CGXX_SCRATCH0_REG 0x1050
		#define CGXX_SCRATCH1_REG 0x1058
		#define CGX_CONST 0x2000

		#define CGX_COMMAND_REG CGXX_SCRATCH1_REG
		#define CGX_EVENT_REG CGXX_SCRATCH0_REG
		#define CGX_CMD_TIMEOUT 2200 /* msecs */

		#define CGX_NVEC 37
		#define CGX_LMAC_FWI 0

		struct cgx_link_event {
		struct cgx_lnk_sts lstat;
		u8 cgx_id;
		u8 lmac_id;
		};

		/**
		* struct cgx_event_cb
		* @notify_link_chg: callback for link change notification
		* @data: data passed to callback function
		*/
		struct cgx_event_cb {
		int (notify_link_chg)(struct cgx_link_event event, void *data);
		void *data;
		};

		extern struct pci_driver cgx_driver;

		int cgx_get_cgx_cnt(void);
		int cgx_get_lmac_cnt(void *cgxd);
		void *cgx_get_pdata(int cgx_id);
		int cgx_lmac_evh_register(struct cgx_event_cb cb, void cgxd, int lmac_id);
		#endif /* CGX_H */

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

0 → 100644

+186 −0

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0
		* Marvell OcteonTx2 CGX driver
		*
		* Copyright (C) 2018 Marvell International Ltd.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*/

		#ifndef __CGX_FW_INTF_H__
		#define __CGX_FW_INTF_H__

		#include <linux/bitops.h>
		#include <linux/bitfield.h>

		#define CGX_FIRMWARE_MAJOR_VER 1
		#define CGX_FIRMWARE_MINOR_VER 0

		#define CGX_EVENT_ACK 1UL

		/* CGX error types. set for cmd response status as CGX_STAT_FAIL */
		enum cgx_error_type {
		CGX_ERR_NONE,
		CGX_ERR_LMAC_NOT_ENABLED,
		CGX_ERR_LMAC_MODE_INVALID,
		CGX_ERR_REQUEST_ID_INVALID,
		CGX_ERR_PREV_ACK_NOT_CLEAR,
		CGX_ERR_PHY_LINK_DOWN,
		CGX_ERR_PCS_RESET_FAIL,
		CGX_ERR_AN_CPT_FAIL,
		CGX_ERR_TX_NOT_IDLE,
		CGX_ERR_RX_NOT_IDLE,
		CGX_ERR_SPUX_BR_BLKLOCK_FAIL,
		CGX_ERR_SPUX_RX_ALIGN_FAIL,
		CGX_ERR_SPUX_TX_FAULT,
		CGX_ERR_SPUX_RX_FAULT,
		CGX_ERR_SPUX_RESET_FAIL,
		CGX_ERR_SPUX_AN_RESET_FAIL,
		CGX_ERR_SPUX_USX_AN_RESET_FAIL,
		CGX_ERR_SMUX_RX_LINK_NOT_OK,
		CGX_ERR_PCS_RECV_LINK_FAIL,
		CGX_ERR_TRAINING_FAIL,
		CGX_ERR_RX_EQU_FAIL,
		CGX_ERR_SPUX_BER_FAIL,
		CGX_ERR_SPUX_RSFEC_ALGN_FAIL, /* = 22 */
		};

		/* LINK speed types */
		enum cgx_link_speed {
		CGX_LINK_NONE,
		CGX_LINK_10M,
		CGX_LINK_100M,
		CGX_LINK_1G,
		CGX_LINK_2HG,
		CGX_LINK_5G,
		CGX_LINK_10G,
		CGX_LINK_20G,
		CGX_LINK_25G,
		CGX_LINK_40G,
		CGX_LINK_50G,
		CGX_LINK_100G,
		CGX_LINK_SPEED_MAX,
		};

		/* REQUEST ID types. Input to firmware */
		enum cgx_cmd_id {
		CGX_CMD_NONE,
		CGX_CMD_GET_FW_VER,
		CGX_CMD_GET_MAC_ADDR,
		CGX_CMD_SET_MTU,
		CGX_CMD_GET_LINK_STS, /* optional to user */
		CGX_CMD_LINK_BRING_UP,
		CGX_CMD_LINK_BRING_DOWN,
		CGX_CMD_INTERNAL_LBK,
		CGX_CMD_EXTERNAL_LBK,
		CGX_CMD_HIGIG,
		CGX_CMD_LINK_STATE_CHANGE,
		CGX_CMD_MODE_CHANGE, /* hot plug support */
		CGX_CMD_INTF_SHUTDOWN,
		CGX_CMD_IRQ_ENABLE,
		CGX_CMD_IRQ_DISABLE,
		};

		/* async event ids */
		enum cgx_evt_id {
		CGX_EVT_NONE,
		CGX_EVT_LINK_CHANGE,
		};

		/* event types - cause of interrupt */
		enum cgx_evt_type {
		CGX_EVT_ASYNC,
		CGX_EVT_CMD_RESP
		};

		enum cgx_stat {
		CGX_STAT_SUCCESS,
		CGX_STAT_FAIL
		};

		enum cgx_cmd_own {
		CGX_CMD_OWN_NS,
		CGX_CMD_OWN_FIRMWARE,
		};

		/* m - bit mask
		* y - value to be written in the bitrange
		* x - input value whose bitrange to be modified
		*/
		#define FIELD_SET(m, y, x) \
		(((x) & ~(m)) \| \
		FIELD_PREP((m), (y)))

		/* scratchx(0) CSR used for ATF->non-secure SW communication.
		* This acts as the status register
		* Provides details on command ack/status, command response, error details
		*/
		#define EVTREG_ACK BIT_ULL(0)
		#define EVTREG_EVT_TYPE BIT_ULL(1)
		#define EVTREG_STAT BIT_ULL(2)
		#define EVTREG_ID GENMASK_ULL(8, 3)

		/* Response to command IDs with command status as CGX_STAT_FAIL
		*
		* Not applicable for commands :
		* CGX_CMD_LINK_BRING_UP/DOWN/CGX_EVT_LINK_CHANGE
		*/
		#define EVTREG_ERRTYPE GENMASK_ULL(18, 9)

		/* Response to cmd ID as CGX_CMD_GET_FW_VER with cmd status as
		* CGX_STAT_SUCCESS
		*/
		#define RESP_MAJOR_VER GENMASK_ULL(12, 9)
		#define RESP_MINOR_VER GENMASK_ULL(16, 13)

		/* Response to cmd ID as CGX_CMD_GET_MAC_ADDR with cmd status as
		* CGX_STAT_SUCCESS
		*/
		#define RESP_MAC_ADDR GENMASK_ULL(56, 9)

		/* Response to cmd ID - CGX_CMD_LINK_BRING_UP/DOWN, event ID CGX_EVT_LINK_CHANGE
		* status can be either CGX_STAT_FAIL or CGX_STAT_SUCCESS
		*
		* In case of CGX_STAT_FAIL, it indicates CGX configuration failed
		* when processing link up/down/change command.
		* Both err_type and current link status will be updated
		*
		* In case of CGX_STAT_SUCCESS, err_type will be CGX_ERR_NONE and current
		* link status will be updated
		*/
		struct cgx_lnk_sts {
		uint64_t reserved1:9;
		uint64_t link_up:1;
		uint64_t full_duplex:1;
		uint64_t speed:4; /* cgx_link_speed */
		uint64_t err_type:10;
		uint64_t reserved2:39;
		};

		#define RESP_LINKSTAT_UP GENMASK_ULL(9, 9)
		#define RESP_LINKSTAT_FDUPLEX GENMASK_ULL(10, 10)
		#define RESP_LINKSTAT_SPEED GENMASK_ULL(14, 11)
		#define RESP_LINKSTAT_ERRTYPE GENMASK_ULL(24, 15)

		/* scratchx(1) CSR used for non-secure SW->ATF communication
		* This CSR acts as a command register
		*/
		#define CMDREG_OWN BIT_ULL(0)
		#define CMDREG_ID GENMASK_ULL(7, 2)

		/* Any command using enable/disable as an argument need
		* to set this bitfield.
		* Ex: Loopback, HiGig...
		*/
		#define CMDREG_ENABLE BIT_ULL(8)

		/* command argument to be passed for cmd ID - CGX_CMD_SET_MTU */
		#define CMDMTU_SIZE GENMASK_ULL(23, 8)

		/* command argument to be passed for cmd ID - CGX_CMD_LINK_CHANGE */
		#define CMDLINKCHANGE_LINKUP BIT_ULL(8)
		#define CMDLINKCHANGE_FULLDPLX BIT_ULL(9)
		#define CMDLINKCHANGE_SPEED GENMASK_ULL(13, 10)

		#endif /* __CGX_FW_INTF_H__ */

drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c

0 → 100644

+97 −0

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0
		/* Marvell OcteonTx2 RVU Admin Function driver
		*
		* Copyright (C) 2018 Marvell International Ltd.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 as
		* published by the Free Software Foundation.
		*/

		#include <linux/types.h>
		#include <linux/module.h>
		#include <linux/pci.h>

		#include "rvu.h"
		#include "cgx.h"

		static inline u8 cgxlmac_id_to_bmap(u8 cgx_id, u8 lmac_id)
		{
		return ((cgx_id & 0xF) << 4) \| (lmac_id & 0xF);
		}

		static void rvu_cgx_pdata(u8 cgx_id, struct rvu rvu)
		{
		if (cgx_id >= rvu->cgx_cnt)
		return NULL;

		return rvu->cgx_idmap[cgx_id];
		}

		static int rvu_map_cgx_lmac_pf(struct rvu *rvu)
		{
		int cgx_cnt = rvu->cgx_cnt;
		int cgx, lmac_cnt, lmac;
		int pf = PF_CGXMAP_BASE;
		int size;

		if (!cgx_cnt)
		return 0;

		if (cgx_cnt > 0xF \|\| MAX_LMAC_PER_CGX > 0xF)
		return -EINVAL;

		/* Alloc map table
		* An additional entry is required since PF id starts from 1 and
		* hence entry at offset 0 is invalid.
		*/
		size = (cgx_cnt * MAX_LMAC_PER_CGX + 1) * sizeof(u8);
		rvu->pf2cgxlmac_map = devm_kzalloc(rvu->dev, size, GFP_KERNEL);
		if (!rvu->pf2cgxlmac_map)
		return -ENOMEM;

		/* Initialize offset 0 with an invalid cgx and lmac id */
		rvu->pf2cgxlmac_map[0] = 0xFF;

		/* Reverse map table */
		rvu->cgxlmac2pf_map = devm_kzalloc(rvu->dev,
		cgx_cnt * MAX_LMAC_PER_CGX * sizeof(u16),
		GFP_KERNEL);
		if (!rvu->cgxlmac2pf_map)
		return -ENOMEM;

		rvu->cgx_mapped_pfs = 0;
		for (cgx = 0; cgx < cgx_cnt; cgx++) {
		lmac_cnt = cgx_get_lmac_cnt(rvu_cgx_pdata(cgx, rvu));
		for (lmac = 0; lmac < lmac_cnt; lmac++, pf++) {
		rvu->pf2cgxlmac_map[pf] = cgxlmac_id_to_bmap(cgx, lmac);
		rvu->cgxlmac2pf_map[CGX_OFFSET(cgx) + lmac] = 1 << pf;
		rvu->cgx_mapped_pfs++;
		}
		}
		return 0;
		}

		int rvu_cgx_probe(struct rvu *rvu)
		{
		int i;

		/* find available cgx ports */
		rvu->cgx_cnt = cgx_get_cgx_cnt();
		if (!rvu->cgx_cnt) {
		dev_info(rvu->dev, "No CGX devices found!\n");
		return -ENODEV;
		}

		rvu->cgx_idmap = devm_kzalloc(rvu->dev, rvu->cgx_cnt * sizeof(void *),
		GFP_KERNEL);
		if (!rvu->cgx_idmap)
		return -ENOMEM;

		/* Initialize the cgxdata table */
		for (i = 0; i < rvu->cgx_cnt; i++)
		rvu->cgx_idmap[i] = cgx_get_pdata(i);

		/* Map CGX LMAC interfaces to RVU PFs */
		return rvu_map_cgx_lmac_pf(rvu);
		}

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