Commit 1434a3d3 authored Nov 19, 2019 by Srinivas Pandruvada Committed by Andy Shevchenko Nov 21, 2019

tools/power/x86/intel-speed-select: Display TRL buckets for just base config level



When only base config level is present, this tool is displaying TRL
(Turbo-ratio-limits) by reading legacy MSR. In this case, also present
core count for TRL by reading MSR 0x1AE.

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

parent 20183ccd

tools/power/x86/intel-speed-select/isst-core.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -681,6 +681,7 @@ int isst_get_process_ctdp(int cpu, int tdp_level, struct isst_pkg_ctdp *pkg_dev)
		}

		isst_get_get_trl_from_msr(cpu, ctdp_level->trl_sse_active_cores);
		isst_get_trl_bucket_info(cpu, &ctdp_level->buckets_info);
		continue;
		}

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