drm/i915: Add documentation to gen9_set_dc_state()

	dev_priv->csr.dc_state = val;

	dev_priv->csr.dc_state = val;

}

}

/**

 * gen9_set_dc_state - set target display C power state

 * @dev_priv: i915 device instance

 * @state: target DC power state

 * - DC_STATE_DISABLE

 * - DC_STATE_EN_UPTO_DC5

 * - DC_STATE_EN_UPTO_DC6

 * - DC_STATE_EN_DC9

 *

 * Signal to DMC firmware/HW the target DC power state passed in @state.

 * DMC/HW can turn off individual display clocks and power rails when entering

 * a deeper DC power state (higher in number) and turns these back when exiting

 * that state to a shallower power state (lower in number). The HW will decide

 * when to actually enter a given state on an on-demand basis, for instance

 * depending on the active state of display pipes. The state of display

 * registers backed by affected power rails are saved/restored as needed.

 *

 * Based on the above enabling a deeper DC power state is asynchronous wrt.

 * enabling it. Disabling a deeper power state is synchronous: for instance

 * setting %DC_STATE_DISABLE won't complete until all HW resources are turned

 * back on and register state is restored. This is guaranteed by the MMIO write

 * to DC_STATE_EN blocking until the state is restored.

 */

static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)

static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)

{

{

	uint32_t val;

	uint32_t val;