iop-adma: add a dummy read to flush next descriptor update (137cb55c) · Commits · 戴 / test

The current dummy read references the wrong address allowing the next descriptor address update to linger in the store buffer and get passed by an 'append' event. This issue was uncovered by the change from strongly-ordered to device memory for the adma registers. Signed-off-by:

Dan Williams <dan.j.williams@intel.com>

drivers/dma/iop-adma.c

+5 −4

Original line number	Diff line number	Diff line
		@@ -411,6 +411,7 @@ iop_adma_tx_submit(struct dma_async_tx_descriptor *tx)
		int slot_cnt;
		int slots_per_op;
		dma_cookie_t cookie;
		dma_addr_t next_dma;

		grp_start = sw_desc->group_head;
		slot_cnt = grp_start->slot_cnt;
		@@ -425,11 +426,11 @@ iop_adma_tx_submit(struct dma_async_tx_descriptor *tx)
		&old_chain_tail->chain_node);

		/* fix up the hardware chain */
		iop_desc_set_next_desc(old_chain_tail, grp_start->async_tx.phys);
		next_dma = grp_start->async_tx.phys;
		iop_desc_set_next_desc(old_chain_tail, next_dma);
		BUG_ON(iop_desc_get_next_desc(old_chain_tail) != next_dma); /* flush */

		/* 1/ don't add pre-chained descriptors
		* 2/ dummy read to flush next_desc write
		*/
		/* check for pre-chained descriptors */
		BUG_ON(iop_desc_get_next_desc(sw_desc));

		/* increment the pending count by the number of slots

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