Commit 13782597 authored by Wen He's avatar Wen He Committed by Shawn Guo
Browse files

arm64: dts: ls1028a: Update the clock providers for the Mali DP500 



In order to maximise performance of the LCD Controller's 64-bit AXI
bus, for any give speed bin of the device, the AXI master interface
clock(ACLK) clock can be up to CPU_frequency/2, which is already
capable of optimal performance. In general, ACLK is always expected
to be equal to CPU_frequency/2. APB slave interface clock(PCLK) and
Main processing clock(PCLK) both are tied to the same clock as ACLK.

This change followed the LS1028A Architecture Specification Manual.

Signed-off-by: default avatarWen He <wen.he_1@nxp.com>
Acked-by: default avatarLi Yang <leoyang.li@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 62b4359c

arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi

+2 −15
Original line number Diff line number Diff line
@@ -86,20 +86,6 @@ 
		clocks = <&osc_27m>;

	};



	aclk: clock-axi {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <650000000>;

		clock-output-names= "aclk";

	};



	pclk: clock-apb {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <650000000>;

		clock-output-names= "pclk";

	};



	reboot {

		compatible ="syscon-reboot";

		regmap = <&dcfg>;
@@ -679,7 +665,8 @@ 
		interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,

			     <0 223 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "DE", "SE";

		clocks = <&dpclk 0>, <&aclk>, <&aclk>, <&pclk>;

		clocks = <&dpclk 0>, <&clockgen 2 2>, <&clockgen 2 2>,

			 <&clockgen 2 2>;

		clock-names = "pxlclk", "mclk", "aclk", "pclk";

		arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;

		arm,malidp-arqos-value = <0xd000d000>;

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