Commit 1374b837 authored by Neil Armstrong's avatar Neil Armstrong
Browse files

drm/meson: dw_hdmi: add resume/suspend hooks 



Add the suspend and resume hooks to:
- reset the whole HDMI glue and HDMI controller on suspend
- re-init the HDMI glue and HDMI controller on resume

The HDMI glue init is refactored to be re-used from the resume hook.

It makes usage of dw_hdmi_resume() to recover a functionnal DDC bus.

Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Tested-by: default avatarKevin Hilman <khilman@baylibre.com>
[narmstrong: fixed typo in commit log, and rebased on drm-misc-next]
Link: https://patchwork.freedesktop.org/patch/msgid/20190827095825.21015-2-narmstrong@baylibre.com
parent b0138364

drivers/gpu/drm/meson/meson_dw_hdmi.c

+76 −34
Original line number Diff line number Diff line
@@ -802,6 +802,47 @@ static bool meson_hdmi_connector_is_available(struct device *dev) 
	return false;

}



static void meson_dw_hdmi_init(struct meson_dw_hdmi *meson_dw_hdmi)

{

	struct meson_drm *priv = meson_dw_hdmi->priv;



	/* Enable clocks */

	regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);



	/* Bring HDMITX MEM output of power down */

	regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0);



	/* Reset HDMITX APB & TX & PHY */

	reset_control_reset(meson_dw_hdmi->hdmitx_apb);

	reset_control_reset(meson_dw_hdmi->hdmitx_ctrl);

	reset_control_reset(meson_dw_hdmi->hdmitx_phy);



	/* Enable APB3 fail on error */

	if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {

		writel_bits_relaxed(BIT(15), BIT(15),

				    meson_dw_hdmi->hdmitx + HDMITX_TOP_CTRL_REG);

		writel_bits_relaxed(BIT(15), BIT(15),

				    meson_dw_hdmi->hdmitx + HDMITX_DWC_CTRL_REG);

	}



	/* Bring out of reset */

	meson_dw_hdmi->data->top_write(meson_dw_hdmi,

				       HDMITX_TOP_SW_RESET,  0);



	msleep(20);



	meson_dw_hdmi->data->top_write(meson_dw_hdmi,

				       HDMITX_TOP_CLK_CNTL, 0xff);



	/* Enable HDMI-TX Interrupt */

	meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,

				       HDMITX_TOP_INTR_CORE);



	meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_MASKN,

				       HDMITX_TOP_INTR_CORE);



}



static int meson_dw_hdmi_bind(struct device *dev, struct device *master,

				void *data)

{
@@ -925,40 +966,7 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master, 


	DRM_DEBUG_DRIVER("encoder initialized\n");



	/* Enable clocks */

	regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);



	/* Bring HDMITX MEM output of power down */

	regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0);



	/* Reset HDMITX APB & TX & PHY */

	reset_control_reset(meson_dw_hdmi->hdmitx_apb);

	reset_control_reset(meson_dw_hdmi->hdmitx_ctrl);

	reset_control_reset(meson_dw_hdmi->hdmitx_phy);



	/* Enable APB3 fail on error */

	if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {

		writel_bits_relaxed(BIT(15), BIT(15),

				    meson_dw_hdmi->hdmitx + HDMITX_TOP_CTRL_REG);

		writel_bits_relaxed(BIT(15), BIT(15),

				    meson_dw_hdmi->hdmitx + HDMITX_DWC_CTRL_REG);

	}



	/* Bring out of reset */

	meson_dw_hdmi->data->top_write(meson_dw_hdmi,

				       HDMITX_TOP_SW_RESET,  0);



	msleep(20);



	meson_dw_hdmi->data->top_write(meson_dw_hdmi,

				       HDMITX_TOP_CLK_CNTL, 0xff);



	/* Enable HDMI-TX Interrupt */

	meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,

				       HDMITX_TOP_INTR_CORE);



	meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_MASKN,

				       HDMITX_TOP_INTR_CORE);

	meson_dw_hdmi_init(meson_dw_hdmi);



	/* Bridge / Connector */
@@ -994,6 +1002,34 @@ static const struct component_ops meson_dw_hdmi_ops = { 
	.unbind	= meson_dw_hdmi_unbind,

};



static int __maybe_unused meson_dw_hdmi_pm_suspend(struct device *dev)

{

	struct meson_dw_hdmi *meson_dw_hdmi = dev_get_drvdata(dev);



	if (!meson_dw_hdmi)

		return 0;



	/* Reset TOP */

	meson_dw_hdmi->data->top_write(meson_dw_hdmi,

				       HDMITX_TOP_SW_RESET, 0);



	return 0;

}



static int __maybe_unused meson_dw_hdmi_pm_resume(struct device *dev)

{

	struct meson_dw_hdmi *meson_dw_hdmi = dev_get_drvdata(dev);



	if (!meson_dw_hdmi)

		return 0;



	meson_dw_hdmi_init(meson_dw_hdmi);



	dw_hdmi_resume(meson_dw_hdmi->hdmi);



	return 0;

}



static int meson_dw_hdmi_probe(struct platform_device *pdev)

{

	return component_add(&pdev->dev, &meson_dw_hdmi_ops);
@@ -1006,6 +1042,11 @@ static int meson_dw_hdmi_remove(struct platform_device *pdev) 
	return 0;

}



static const struct dev_pm_ops meson_dw_hdmi_pm_ops = {

	SET_SYSTEM_SLEEP_PM_OPS(meson_dw_hdmi_pm_suspend,

				meson_dw_hdmi_pm_resume)

};



static const struct of_device_id meson_dw_hdmi_of_table[] = {

	{ .compatible = "amlogic,meson-gxbb-dw-hdmi",

	  .data = &meson_dw_hdmi_gx_data },
@@ -1025,6 +1066,7 @@ static struct platform_driver meson_dw_hdmi_platform_driver = { 
	.driver		= {

		.name		= DRIVER_NAME,

		.of_match_table	= meson_dw_hdmi_of_table,

		.pm = &meson_dw_hdmi_pm_ops,

	},

};

module_platform_driver(meson_dw_hdmi_platform_driver);

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