Commit 134b480f authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: Add support for programming the FMT blocks 



The FMT blocks control how data is sent from the backend
of the display pipe to to monitor.  Proper set up of the
FMT blocks are required for 30bpp formats.  Additionally,
dithering can be enabled on for better display with 18 and
24bpp displays.  The exception is LVDS/eDP which atom
takes care of in the SelectCRTC_Source table.  For now
just enable truncation until we test dithering more.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9d6104e0

drivers/gpu/drm/radeon/atombios_encoders.c

+9 −0
Original line number Diff line number Diff line
@@ -2392,6 +2392,15 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 


	/* this is needed for the pll/ss setup to work correctly in some cases */

	atombios_set_encoder_crtc_source(encoder);

	/* set up the FMT blocks */

	if (ASIC_IS_DCE8(rdev))

		dce8_program_fmt(encoder);

	else if (ASIC_IS_DCE4(rdev))

		dce4_program_fmt(encoder);

	else if (ASIC_IS_DCE3(rdev))

		dce3_program_fmt(encoder);

	else if (ASIC_IS_AVIVO(rdev))

		avivo_program_fmt(encoder);

}



static void radeon_atom_encoder_commit(struct drm_encoder *encoder)

drivers/gpu/drm/radeon/cik.c

+61 −0
Original line number Diff line number Diff line
@@ -7418,6 +7418,67 @@ void cik_fini(struct radeon_device *rdev) 
	rdev->bios = NULL;

}



void dce8_program_fmt(struct drm_encoder *encoder)

{

	struct drm_device *dev = encoder->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);

	int bpc = 0;

	u32 tmp = 0;

	bool dither = false;



	if (connector)

		bpc = radeon_get_monitor_bpc(connector);



	/* LVDS/eDP FMT is set up by atom */

	if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)

		return;



	/* not needed for analog */

	if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||

	    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))

		return;



	if (bpc == 0)

		return;



	switch (bpc) {

	case 6:

		if (dither)

			/* XXX sort out optimal dither settings */

			tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |

				FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(0));

		else

			tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(0));

		break;

	case 8:

		if (dither)

			/* XXX sort out optimal dither settings */

			tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |

				FMT_RGB_RANDOM_ENABLE |

				FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(1));

		else

			tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(1));

		break;

	case 10:

		if (dither)

			/* XXX sort out optimal dither settings */

			tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |

				FMT_RGB_RANDOM_ENABLE |

				FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(2));

		else

			tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(2));

		break;

	default:

		/* not needed */

		break;

	}



	WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);

}



/* display watermark setup */

/**

 * dce8_line_buffer_adjust - Set up the line buffer

drivers/gpu/drm/radeon/cikd.h

+33 −0
Original line number Diff line number Diff line
@@ -906,6 +906,39 @@ 
#define DPG_PIPE_STUTTER_CONTROL                          0x6cd4

#       define STUTTER_ENABLE                             (1 << 0)



/* DCE8 FMT blocks */

#define FMT_DYNAMIC_EXP_CNTL                 0x6fb4

#       define FMT_DYNAMIC_EXP_EN            (1 << 0)

#       define FMT_DYNAMIC_EXP_MODE          (1 << 4)

        /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */

#define FMT_CONTROL                          0x6fb8

#       define FMT_PIXEL_ENCODING            (1 << 16)

        /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */

#define FMT_BIT_DEPTH_CONTROL                0x6fc8

#       define FMT_TRUNCATE_EN               (1 << 0)

#       define FMT_TRUNCATE_MODE             (1 << 1)

#       define FMT_TRUNCATE_DEPTH(x)         ((x) << 4) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */

#       define FMT_SPATIAL_DITHER_EN         (1 << 8)

#       define FMT_SPATIAL_DITHER_MODE(x)    ((x) << 9)

#       define FMT_SPATIAL_DITHER_DEPTH(x)   ((x) << 11) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */

#       define FMT_FRAME_RANDOM_ENABLE       (1 << 13)

#       define FMT_RGB_RANDOM_ENABLE         (1 << 14)

#       define FMT_HIGHPASS_RANDOM_ENABLE    (1 << 15)

#       define FMT_TEMPORAL_DITHER_EN        (1 << 16)

#       define FMT_TEMPORAL_DITHER_DEPTH(x)  ((x) << 17) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */

#       define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)

#       define FMT_TEMPORAL_LEVEL            (1 << 24)

#       define FMT_TEMPORAL_DITHER_RESET     (1 << 25)

#       define FMT_25FRC_SEL(x)              ((x) << 26)

#       define FMT_50FRC_SEL(x)              ((x) << 28)

#       define FMT_75FRC_SEL(x)              ((x) << 30)

#define FMT_CLAMP_CONTROL                    0x6fe4

#       define FMT_CLAMP_DATA_EN             (1 << 0)

#       define FMT_CLAMP_COLOR_FORMAT(x)     ((x) << 16)

#       define FMT_CLAMP_6BPC                0

#       define FMT_CLAMP_8BPC                1

#       define FMT_CLAMP_10BPC               2



#define	GRBM_CNTL					0x8000

#define		GRBM_READ_TIMEOUT(x)				((x) << 0)

drivers/gpu/drm/radeon/evergreen.c

+53 −0
Original line number Diff line number Diff line
@@ -1193,6 +1193,59 @@ void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev) 
	}

}



void dce4_program_fmt(struct drm_encoder *encoder)

{

	struct drm_device *dev = encoder->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);

	int bpc = 0;

	u32 tmp = 0;

	bool dither = false;



	if (connector)

		bpc = radeon_get_monitor_bpc(connector);



	/* LVDS/eDP FMT is set up by atom */

	if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)

		return;



	/* not needed for analog */

	if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||

	    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))

		return;



	if (bpc == 0)

		return;



	switch (bpc) {

	case 6:

		if (dither)

			/* XXX sort out optimal dither settings */

			tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |

				FMT_SPATIAL_DITHER_EN);

		else

			tmp |= FMT_TRUNCATE_EN;

		break;

	case 8:

		if (dither)

			/* XXX sort out optimal dither settings */

			tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |

				FMT_RGB_RANDOM_ENABLE |

				FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH);

		else

			tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);

		break;

	case 10:

	default:

		/* not needed */

		break;

	}



	WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);

}



static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc)

{

	if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)

drivers/gpu/drm/radeon/evergreend.h

+32 −0
Original line number Diff line number Diff line
@@ -1312,6 +1312,38 @@ 
#       define DC_HPDx_RX_INT_TIMER(x)                    ((x) << 16)

#       define DC_HPDx_EN                                 (1 << 28)



/* DCE4/5/6 FMT blocks */

#define FMT_DYNAMIC_EXP_CNTL                 0x6fb4

#       define FMT_DYNAMIC_EXP_EN            (1 << 0)

#       define FMT_DYNAMIC_EXP_MODE          (1 << 4)

        /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */

#define FMT_CONTROL                          0x6fb8

#       define FMT_PIXEL_ENCODING            (1 << 16)

        /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */

#define FMT_BIT_DEPTH_CONTROL                0x6fc8

#       define FMT_TRUNCATE_EN               (1 << 0)

#       define FMT_TRUNCATE_DEPTH            (1 << 4)

#       define FMT_SPATIAL_DITHER_EN         (1 << 8)

#       define FMT_SPATIAL_DITHER_MODE(x)    ((x) << 9)

#       define FMT_SPATIAL_DITHER_DEPTH      (1 << 12)

#       define FMT_FRAME_RANDOM_ENABLE       (1 << 13)

#       define FMT_RGB_RANDOM_ENABLE         (1 << 14)

#       define FMT_HIGHPASS_RANDOM_ENABLE    (1 << 15)

#       define FMT_TEMPORAL_DITHER_EN        (1 << 16)

#       define FMT_TEMPORAL_DITHER_DEPTH     (1 << 20)

#       define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)

#       define FMT_TEMPORAL_LEVEL            (1 << 24)

#       define FMT_TEMPORAL_DITHER_RESET     (1 << 25)

#       define FMT_25FRC_SEL(x)              ((x) << 26)

#       define FMT_50FRC_SEL(x)              ((x) << 28)

#       define FMT_75FRC_SEL(x)              ((x) << 30)

#define FMT_CLAMP_CONTROL                    0x6fe4

#       define FMT_CLAMP_DATA_EN             (1 << 0)

#       define FMT_CLAMP_COLOR_FORMAT(x)     ((x) << 16)

#       define FMT_CLAMP_6BPC                0

#       define FMT_CLAMP_8BPC                1

#       define FMT_CLAMP_10BPC               2



/* ASYNC DMA */

#define DMA_RB_RPTR                                       0xd008

#define DMA_RB_WPTR                                       0xd00c

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