dt-bindings: phy: Convert UniPhier USB3-PHY conroller to json-schema (134ab284) · Commits · 戴 / test

Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Socionext UniPhier USB3 High-Speed (HS) PHY

		description: \|
		This describes the devicetree bindings for PHY interfaces built into
		USB3 controller implemented on Socionext UniPhier SoCs.
		Although the controller includes High-Speed PHY and Super-Speed PHY,
		this describes about High-Speed PHY.

		maintainers:
		- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

		properties:
		compatible:
		enum:
		- socionext,uniphier-pro5-usb3-hsphy
		- socionext,uniphier-pxs2-usb3-hsphy
		- socionext,uniphier-ld20-usb3-hsphy
		- socionext,uniphier-pxs3-usb3-hsphy

		reg:
		description: PHY register region (offset and length)

		"#phy-cells":
		const: 0

		clocks:
		minItems: 1
		maxItems: 2

		clock-names:
		oneOf:
		- const: link # for PXs2
		- items: # for PXs3
		- const: link
		- const: phy

		resets:
		maxItems: 2

		reset-names:
		items:
		- const: link
		- const: phy

		vbus-supply:
		description: A phandle to the regulator for USB VBUS

		nvmem-cells:
		maxItems: 3
		description:
		Phandles to nvmem cell that contains the trimming data.
		Available only for HS-PHY implemented on LD20 and PXs3, and
		if unspecified, default value is used.

		nvmem-cell-names:
		items:
		- const: rterm
		- const: sel_t
		- const: hs_i
		description:
		Should be the following names, which correspond to each nvmem-cells.
		All of the 3 parameters associated with the above names are
		required for each port, if any one is omitted, the trimming data
		of the port will not be set at all.

		required:
		- compatible
		- reg
		- "#phy-cells"
		- clocks
		- clock-names
		- resets
		- reset-names

		additionalProperties: false

		examples:
		- \|
		usb-glue@65b00000 {
		compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x65b00000 0x400>;

		usb_hsphy0: hs-phy@200 {
		compatible = "socionext,uniphier-ld20-usb3-hsphy";
		reg = <0x200 0x10>;
		#phy-cells = <0>;
		clock-names = "link", "phy";
		clocks = <&sys_clk 14>, <&sys_clk 16>;
		reset-names = "link", "phy";
		resets = <&sys_rst 14>, <&sys_rst 16>;
		vbus-supply = <&usb_vbus0>;
		nvmem-cell-names = "rterm", "sel_t", "hs_i";
		nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>;
		};
		};

Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Socionext UniPhier USB3 Super-Speed (SS) PHY

		description: \|
		This describes the devicetree bindings for PHY interfaces built into
		USB3 controller implemented on Socionext UniPhier SoCs.
		Although the controller includes High-Speed PHY and Super-Speed PHY,
		this describes about Super-Speed PHY.

		maintainers:
		- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

		properties:
		compatible:
		enum:
		- socionext,uniphier-pro4-usb3-ssphy
		- socionext,uniphier-pro5-usb3-ssphy
		- socionext,uniphier-pxs2-usb3-ssphy
		- socionext,uniphier-ld20-usb3-ssphy
		- socionext,uniphier-pxs3-usb3-ssphy

		reg:
		description: PHY register region (offset and length)

		"#phy-cells":
		const: 0

		clocks:
		minItems: 2
		maxItems: 3

		clock-names:
		oneOf:
		- items: # for Pro4, Pro5
		- const: gio
		- const: link
		- items: # for PXs3 with phy-ext
		- const: link
		- const: phy
		- const: phy-ext
		- items: # for others
		- const: link
		- const: phy

		resets:
		maxItems: 2

		reset-names:
		oneOf:
		- items: # for Pro4,Pro5
		- const: gio
		- const: link
		- items: # for others
		- const: link
		- const: phy

		vbus-supply:
		description: A phandle to the regulator for USB VBUS

		required:
		- compatible
		- reg
		- "#phy-cells"
		- clocks
		- clock-names
		- resets
		- reset-names
		- vbus-supply

		additionalProperties: false

		examples:
		- \|
		usb-glue@65b00000 {
		compatible = "socionext,uniphier-ld20-dwc3-glue",
		"simple-mfd";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x65b00000 0x400>;

		usb_ssphy0: ss-phy@300 {
		compatible = "socionext,uniphier-ld20-usb3-ssphy";
		reg = <0x300 0x10>;
		#phy-cells = <0>;
		clock-names = "link", "phy";
		clocks = <&sys_clk 14>, <&sys_clk 16>;
		reset-names = "link", "phy";
		resets = <&sys_rst 14>, <&sys_rst 16>;
		vbus-supply = <&usb_vbus0>;
		};
		};

Documentation/devicetree/bindings/phy/uniphier-usb3-hsphy.txt

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		Socionext UniPhier USB3 High-Speed (HS) PHY

		This describes the devicetree bindings for PHY interfaces built into
		USB3 controller implemented on Socionext UniPhier SoCs.
		Although the controller includes High-Speed PHY and Super-Speed PHY,
		this describes about High-Speed PHY.

		Required properties:
		- compatible: Should contain one of the following:
		"socionext,uniphier-pro5-usb3-hsphy" - for Pro5 SoC
		"socionext,uniphier-pxs2-usb3-hsphy" - for PXs2 SoC
		"socionext,uniphier-ld20-usb3-hsphy" - for LD20 SoC
		"socionext,uniphier-pxs3-usb3-hsphy" - for PXs3 SoC
		- reg: Specifies offset and length of the register set for the device.
		- #phy-cells: Should be 0.
		- clocks: A list of phandles to the clock gate for USB3 glue layer.
		According to the clock-names, appropriate clocks are required.
		- clock-names: Should contain the following:
		"gio", "link" - for Pro5 SoC
		"phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional.
		"phy", "link" - for others
		- resets: A list of phandles to the reset control for USB3 glue layer.
		According to the reset-names, appropriate resets are required.
		- reset-names: Should contain the following:
		"gio", "link" - for Pro5 SoC
		"phy", "link" - for others

		Optional properties:
		- vbus-supply: A phandle to the regulator for USB VBUS.
		- nvmem-cells: Phandles to nvmem cell that contains the trimming data.
		Available only for HS-PHY implemented on LD20 and PXs3, and
		if unspecified, default value is used.
		- nvmem-cell-names: Should be the following names, which correspond to
		each nvmem-cells.
		All of the 3 parameters associated with the following names are
		required for each port, if any one is omitted, the trimming data
		of the port will not be set at all.
		"rterm", "sel_t", "hs_i" - Each cell name for phy parameters

		Refer to phy/phy-bindings.txt for the generic PHY binding properties.

		Example:

		usb-glue@65b00000 {
		compatible = "socionext,uniphier-ld20-dwc3-glue",
		"simple-mfd";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x65b00000 0x400>;

		usb_vbus0: regulator {
		...
		};

		usb_hsphy0: hs-phy@200 {
		compatible = "socionext,uniphier-ld20-usb3-hsphy";
		reg = <0x200 0x10>;
		#phy-cells = <0>;
		clock-names = "link", "phy";
		clocks = <&sys_clk 14>, <&sys_clk 16>;
		reset-names = "link", "phy";
		resets = <&sys_rst 14>, <&sys_rst 16>;
		vbus-supply = <&usb_vbus0>;
		nvmem-cell-names = "rterm", "sel_t", "hs_i";
		nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
		<&usb_hs_i0>;
		};
		...
		};

Documentation/devicetree/bindings/phy/uniphier-usb3-ssphy.txt

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		Socionext UniPhier USB3 Super-Speed (SS) PHY

		This describes the devicetree bindings for PHY interfaces built into
		USB3 controller implemented on Socionext UniPhier SoCs.
		Although the controller includes High-Speed PHY and Super-Speed PHY,
		this describes about Super-Speed PHY.

		Required properties:
		- compatible: Should contain one of the following:
		"socionext,uniphier-pro4-usb3-ssphy" - for Pro4 SoC
		"socionext,uniphier-pro5-usb3-ssphy" - for Pro5 SoC
		"socionext,uniphier-pxs2-usb3-ssphy" - for PXs2 SoC
		"socionext,uniphier-ld20-usb3-ssphy" - for LD20 SoC
		"socionext,uniphier-pxs3-usb3-ssphy" - for PXs3 SoC
		- reg: Specifies offset and length of the register set for the device.
		- #phy-cells: Should be 0.
		- clocks: A list of phandles to the clock gate for USB3 glue layer.
		According to the clock-names, appropriate clocks are required.
		- clock-names:
		"gio", "link" - for Pro4 and Pro5 SoC
		"phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional.
		"phy", "link" - for others
		- resets: A list of phandles to the reset control for USB3 glue layer.
		According to the reset-names, appropriate resets are required.
		- reset-names:
		"gio", "link" - for Pro4 and Pro5 SoC
		"phy", "link" - for others

		Optional properties:
		- vbus-supply: A phandle to the regulator for USB VBUS.

		Refer to phy/phy-bindings.txt for the generic PHY binding properties.

		Example:

		usb-glue@65b00000 {
		compatible = "socionext,uniphier-ld20-dwc3-glue",
		"simple-mfd";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x65b00000 0x400>;

		usb_vbus0: regulator {
		...
		};

		usb_ssphy0: ss-phy@300 {
		compatible = "socionext,uniphier-ld20-usb3-ssphy";
		reg = <0x300 0x10>;
		#phy-cells = <0>;
		clock-names = "link", "phy";
		clocks = <&sys_clk 14>, <&sys_clk 16>;
		reset-names = "link", "phy";
		resets = <&sys_rst 14>, <&sys_rst 16>;
		vbus-supply = <&usb_vbus0>;
		};
		...
		};

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