Commit 1326a92c authored by Maarten Lankhorst's avatar Maarten Lankhorst
Browse files

drm/i915: Perform automated conversions for crtc uapi/hw split, base -> hw. 



Split up crtc_state->base to hw where appropriate. This is done using the following patch:

@@
struct intel_crtc_state *T;
identifier x =~ "^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";
@@
-T->base.x
+T->hw.x

@@
struct drm_crtc_state *T;
identifier x =~ "^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";
@@
-to_intel_crtc_state(T)->base.x
+to_intel_crtc_state(T)->hw.x

Signed-off-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191031112610.27608-4-maarten.lankhorst@linux.intel.com
parent aa42a50a

drivers/gpu/drm/i915/display/icl_dsi.c

+6 −6
Original line number Diff line number Diff line
@@ -276,7 +276,7 @@ static void configure_dual_link_mode(struct intel_encoder *encoder, 


	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {

		const struct drm_display_mode *adjusted_mode =

					&pipe_config->base.adjusted_mode;

					&pipe_config->hw.adjusted_mode;

		u32 dss_ctl2;

		u16 hactive = adjusted_mode->crtc_hdisplay;

		u16 dl_buffer_depth;
@@ -768,7 +768,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);

	const struct drm_display_mode *adjusted_mode =

					&pipe_config->base.adjusted_mode;

					&pipe_config->hw.adjusted_mode;

	enum port port;

	enum transcoder dsi_trans;

	/* horizontal timings */
@@ -1216,7 +1216,7 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder, 
{

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);

	struct drm_display_mode *adjusted_mode =

					&pipe_config->base.adjusted_mode;

					&pipe_config->hw.adjusted_mode;



	if (intel_dsi->dual_link) {

		adjusted_mode->crtc_hdisplay *= 2;
@@ -1249,9 +1249,9 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder, 
	pipe_config->port_clock =

		cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);



	pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;

	pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;

	if (intel_dsi->dual_link)

		pipe_config->base.adjusted_mode.crtc_clock *= 2;

		pipe_config->hw.adjusted_mode.crtc_clock *= 2;



	gen11_dsi_get_timings(encoder, pipe_config);

	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
@@ -1269,7 +1269,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder, 
	const struct drm_display_mode *fixed_mode =

					intel_connector->panel.fixed_mode;

	struct drm_display_mode *adjusted_mode =

					&pipe_config->base.adjusted_mode;

					&pipe_config->hw.adjusted_mode;



	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;

	intel_fixed_panel_mode(fixed_mode, adjusted_mode);

drivers/gpu/drm/i915/display/intel_audio.c

+2 −2
Original line number Diff line number Diff line
@@ -234,7 +234,7 @@ static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = { 
static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)

{

	const struct drm_display_mode *adjusted_mode =

		&crtc_state->base.adjusted_mode;

		&crtc_state->hw.adjusted_mode;

	int i;



	for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
@@ -695,7 +695,7 @@ void intel_audio_codec_enable(struct intel_encoder *encoder, 
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	struct drm_connector *connector = conn_state->connector;

	const struct drm_display_mode *adjusted_mode =

		&crtc_state->base.adjusted_mode;

		&crtc_state->hw.adjusted_mode;

	enum port port = encoder->port;

	enum pipe pipe = crtc->pipe;

drivers/gpu/drm/i915/display/intel_cdclk.c

+4 −4
Original line number Diff line number Diff line
@@ -1937,7 +1937,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) 
		to_i915(crtc_state->base.crtc->dev);

	int min_cdclk;



	if (!crtc_state->base.enable)

	if (!crtc_state->hw.enable)

		return 0;



	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
@@ -2074,7 +2074,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) 
	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {

		int ret;



		if (crtc_state->base.enable)

		if (crtc_state->hw.enable)

			min_voltage_level = crtc_state->min_voltage_level;

		else

			min_voltage_level = 0;
@@ -2168,7 +2168,7 @@ static int skl_dpll0_vco(struct intel_atomic_state *state) 
		vco = dev_priv->skl_preferred_vco_freq;



	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {

		if (!crtc_state->base.enable)

		if (!crtc_state->hw.enable)

			continue;



		if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
@@ -2281,7 +2281,7 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state) 
		if (IS_ERR(crtc_state))

			return PTR_ERR(crtc_state);



		if (!crtc_state->base.active ||

		if (!crtc_state->hw.active ||

		    drm_atomic_crtc_needs_modeset(&crtc_state->base))

			continue;

drivers/gpu/drm/i915/display/intel_color.c

+54 −54
Original line number Diff line number Diff line
@@ -117,10 +117,10 @@ static bool lut_is_legacy(const struct drm_property_blob *lut) 


static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state)

{

	return !crtc_state->base.degamma_lut &&

		!crtc_state->base.ctm &&

		crtc_state->base.gamma_lut &&

		lut_is_legacy(crtc_state->base.gamma_lut);

	return !crtc_state->hw.degamma_lut &&

		!crtc_state->hw.ctm &&

		crtc_state->hw.gamma_lut &&

		lut_is_legacy(crtc_state->hw.gamma_lut);

}



/*
@@ -219,7 +219,7 @@ static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state) 
static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,

				u16 coeffs[9])

{

	const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;

	const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;

	const u64 *input;

	u64 temp[9];

	int i;
@@ -274,7 +274,7 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state) 
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	bool limited_color_range = ilk_csc_limited_range(crtc_state);



	if (crtc_state->base.ctm) {

	if (crtc_state->hw.ctm) {

		u16 coeff[9];



		ilk_csc_convert_ctm(crtc_state, coeff);
@@ -312,7 +312,7 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state) 
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);



	if (crtc_state->base.ctm) {

	if (crtc_state->hw.ctm) {

		u16 coeff[9];



		ilk_csc_convert_ctm(crtc_state, coeff);
@@ -342,8 +342,8 @@ static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state 
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;



	if (crtc_state->base.ctm) {

		const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;

	if (crtc_state->hw.ctm) {

		const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;

		u16 coeffs[9] = {};

		int i;
@@ -435,7 +435,7 @@ static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state, 


static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)

{

	i9xx_load_luts_internal(crtc_state, crtc_state->base.gamma_lut);

	i9xx_load_luts_internal(crtc_state, crtc_state->hw.gamma_lut);

}



static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
@@ -525,7 +525,7 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc, 
static void i965_load_luts(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;

	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;



	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)

		i9xx_load_luts(crtc_state);
@@ -548,7 +548,7 @@ static void ilk_load_lut_10(struct intel_crtc *crtc, 
static void ilk_load_luts(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;

	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;



	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)

		i9xx_load_luts(crtc_state);
@@ -655,8 +655,8 @@ static void ivb_load_lut_ext_max(struct intel_crtc *crtc) 
static void ivb_load_luts(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;

	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;

	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;

	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;



	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {

		i9xx_load_luts(crtc_state);
@@ -678,8 +678,8 @@ static void ivb_load_luts(const struct intel_crtc_state *crtc_state) 
static void bdw_load_luts(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;

	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;

	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;

	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;



	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {

		i9xx_load_luts(crtc_state);
@@ -704,7 +704,7 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) 
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;

	const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;

	const struct drm_color_lut *lut = crtc_state->base.degamma_lut->data;

	const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;

	u32 i;



	/*
@@ -766,7 +766,7 @@ static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_stat 


static void glk_load_luts(const struct intel_crtc_state *crtc_state)

{

	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;

	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);



	/*
@@ -777,7 +777,7 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state) 
	 * the degama LUT so that we don't have to reload

	 * it every time the pipe CSC is being enabled.

	 */

	if (crtc_state->base.degamma_lut)

	if (crtc_state->hw.degamma_lut)

		glk_load_degamma_lut(crtc_state);

	else

		glk_load_degamma_lut_linear(crtc_state);
@@ -823,7 +823,7 @@ static void 
icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	const struct drm_property_blob *blob = crtc_state->base.gamma_lut;

	const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;

	const struct drm_color_lut *lut = blob->data;

	struct intel_dsb *dsb = intel_dsb_get(crtc);

	enum pipe pipe = crtc->pipe;
@@ -855,7 +855,7 @@ static void 
icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	const struct drm_property_blob *blob = crtc_state->base.gamma_lut;

	const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;

	const struct drm_color_lut *lut = blob->data;

	const struct drm_color_lut *entry;

	struct intel_dsb *dsb = intel_dsb_get(crtc);
@@ -910,11 +910,11 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state) 


static void icl_load_luts(const struct intel_crtc_state *crtc_state)

{

	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;

	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	struct intel_dsb *dsb = intel_dsb_get(crtc);



	if (crtc_state->base.degamma_lut)

	if (crtc_state->hw.degamma_lut)

		glk_load_degamma_lut(crtc_state);



	switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
@@ -991,8 +991,8 @@ static void chv_load_cgm_gamma(struct intel_crtc *crtc, 
static void chv_load_luts(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;

	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;

	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;

	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;



	cherryview_load_csc_matrix(crtc_state);
@@ -1063,7 +1063,7 @@ intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state) 
		intel_atomic_get_old_crtc_state(state, crtc);

	struct intel_plane *plane;



	if (!new_crtc_state->base.active ||

	if (!new_crtc_state->hw.active ||

	    drm_atomic_crtc_needs_modeset(&new_crtc_state->base))

		return 0;
@@ -1107,8 +1107,8 @@ static int check_lut_size(const struct drm_property_blob *lut, int expected) 
static int check_luts(const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);

	const struct drm_property_blob *gamma_lut = crtc_state->base.gamma_lut;

	const struct drm_property_blob *degamma_lut = crtc_state->base.degamma_lut;

	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;

	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;

	int gamma_length, degamma_length;

	u32 gamma_tests, degamma_tests;
@@ -1156,7 +1156,7 @@ static int i9xx_color_check(struct intel_crtc_state *crtc_state) 
		return ret;



	crtc_state->gamma_enable =

		crtc_state->base.gamma_lut &&

		crtc_state->hw.gamma_lut &&

		!crtc_state->c8_planes;



	crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state);
@@ -1175,11 +1175,11 @@ static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state) 
	if (crtc_state_is_legacy_gamma(crtc_state))

		return 0;



	if (crtc_state->base.degamma_lut)

	if (crtc_state->hw.degamma_lut)

		cgm_mode |= CGM_PIPE_MODE_DEGAMMA;

	if (crtc_state->base.ctm)

	if (crtc_state->hw.ctm)

		cgm_mode |= CGM_PIPE_MODE_CSC;

	if (crtc_state->base.gamma_lut)

	if (crtc_state->hw.gamma_lut)

		cgm_mode |= CGM_PIPE_MODE_GAMMA;



	return cgm_mode;
@@ -1253,7 +1253,7 @@ static int ilk_color_check(struct intel_crtc_state *crtc_state) 
		return ret;



	crtc_state->gamma_enable =

		crtc_state->base.gamma_lut &&

		crtc_state->hw.gamma_lut &&

		!crtc_state->c8_planes;



	/*
@@ -1279,8 +1279,8 @@ static u32 ivb_gamma_mode(const struct intel_crtc_state *crtc_state) 
	if (!crtc_state->gamma_enable ||

	    crtc_state_is_legacy_gamma(crtc_state))

		return GAMMA_MODE_MODE_8BIT;

	else if (crtc_state->base.gamma_lut &&

		 crtc_state->base.degamma_lut)

	else if (crtc_state->hw.gamma_lut &&

		 crtc_state->hw.degamma_lut)

		return GAMMA_MODE_MODE_SPLIT;

	else

		return GAMMA_MODE_MODE_10BIT;
@@ -1294,7 +1294,7 @@ static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state) 
	 * CSC comes after the LUT in degamma, RGB->YCbCr,

	 * and RGB full->limited range mode.

	 */

	if (crtc_state->base.degamma_lut ||

	if (crtc_state->hw.degamma_lut ||

	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||

	    limited_color_range)

		return 0;
@@ -1312,13 +1312,13 @@ static int ivb_color_check(struct intel_crtc_state *crtc_state) 
		return ret;



	crtc_state->gamma_enable =

		(crtc_state->base.gamma_lut ||

		 crtc_state->base.degamma_lut) &&

		(crtc_state->hw.gamma_lut ||

		 crtc_state->hw.degamma_lut) &&

		!crtc_state->c8_planes;



	crtc_state->csc_enable =

		crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||

		crtc_state->base.ctm || limited_color_range;

		crtc_state->hw.ctm || limited_color_range;



	crtc_state->gamma_mode = ivb_gamma_mode(crtc_state);
@@ -1349,14 +1349,14 @@ static int glk_color_check(struct intel_crtc_state *crtc_state) 
		return ret;



	crtc_state->gamma_enable =

		crtc_state->base.gamma_lut &&

		crtc_state->hw.gamma_lut &&

		!crtc_state->c8_planes;



	/* On GLK+ degamma LUT is controlled by csc_enable */

	crtc_state->csc_enable =

		crtc_state->base.degamma_lut ||

		crtc_state->hw.degamma_lut ||

		crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||

		crtc_state->base.ctm || crtc_state->limited_color_range;

		crtc_state->hw.ctm || crtc_state->limited_color_range;



	crtc_state->gamma_mode = glk_gamma_mode(crtc_state);
@@ -1373,14 +1373,14 @@ static u32 icl_gamma_mode(const struct intel_crtc_state *crtc_state) 
{

	u32 gamma_mode = 0;



	if (crtc_state->base.degamma_lut)

	if (crtc_state->hw.degamma_lut)

		gamma_mode |= PRE_CSC_GAMMA_ENABLE;



	if (crtc_state->base.gamma_lut &&

	if (crtc_state->hw.gamma_lut &&

	    !crtc_state->c8_planes)

		gamma_mode |= POST_CSC_GAMMA_ENABLE;



	if (!crtc_state->base.gamma_lut ||

	if (!crtc_state->hw.gamma_lut ||

	    crtc_state_is_legacy_gamma(crtc_state))

		gamma_mode |= GAMMA_MODE_MODE_8BIT;

	else
@@ -1393,7 +1393,7 @@ static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state) 
{

	u32 csc_mode = 0;



	if (crtc_state->base.ctm)

	if (crtc_state->hw.ctm)

		csc_mode |= ICL_CSC_ENABLE;



	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
@@ -1622,7 +1622,7 @@ static void i9xx_read_luts(struct intel_crtc_state *crtc_state) 
	if (!crtc_state->gamma_enable)

		return;



	crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);

	crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);

}



static struct drm_property_blob *
@@ -1672,9 +1672,9 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state) 
		return;



	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)

		crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);

		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);

	else

		crtc_state->base.gamma_lut = i965_read_lut_10p6(crtc_state);

		crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc_state);

}



static struct drm_property_blob *
@@ -1714,7 +1714,7 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state) 
static void chv_read_luts(struct intel_crtc_state *crtc_state)

{

	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)

		crtc_state->base.gamma_lut = chv_read_cgm_lut(crtc_state);

		crtc_state->hw.gamma_lut = chv_read_cgm_lut(crtc_state);

	else

		i965_read_luts(crtc_state);

}
@@ -1761,9 +1761,9 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state) 
		return;



	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)

		crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);

		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);

	else

		crtc_state->base.gamma_lut = ilk_read_lut_10(crtc_state);

		crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc_state);

}



static struct drm_property_blob *
@@ -1810,9 +1810,9 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state) 
		return;



	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)

		crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);

		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);

	else

		crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));

		crtc_state->hw.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));

}



void intel_color_init(struct intel_crtc *crtc)

drivers/gpu/drm/i915/display/intel_crt.c

+9 −9
Original line number Diff line number Diff line
@@ -132,9 +132,9 @@ static void intel_crt_get_config(struct intel_encoder *encoder, 
{

	pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);



	pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);

	pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);



	pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;

	pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;

}



static void hsw_crt_get_config(struct intel_encoder *encoder,
@@ -144,13 +144,13 @@ static void hsw_crt_get_config(struct intel_encoder *encoder, 


	intel_ddi_get_config(encoder, pipe_config);



	pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |

	pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |

					      DRM_MODE_FLAG_NHSYNC |

					      DRM_MODE_FLAG_PVSYNC |

					      DRM_MODE_FLAG_NVSYNC);

	pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);

	pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);



	pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);

	pipe_config->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv);

}



/* Note: The caller is required to filter out dpms modes not supported by the
@@ -162,7 +162,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, 
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_crt *crt = intel_encoder_to_crt(encoder);

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);

	const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;

	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;

	u32 adpa;



	if (INTEL_GEN(dev_priv) >= 5)
@@ -358,7 +358,7 @@ static int intel_crt_compute_config(struct intel_encoder *encoder, 
				    struct drm_connector_state *conn_state)

{

	struct drm_display_mode *adjusted_mode =

		&pipe_config->base.adjusted_mode;

		&pipe_config->hw.adjusted_mode;



	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)

		return -EINVAL;
@@ -373,7 +373,7 @@ static int pch_crt_compute_config(struct intel_encoder *encoder, 
				  struct drm_connector_state *conn_state)

{

	struct drm_display_mode *adjusted_mode =

		&pipe_config->base.adjusted_mode;

		&pipe_config->hw.adjusted_mode;



	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)

		return -EINVAL;
@@ -390,7 +390,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder, 
{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct drm_display_mode *adjusted_mode =

		&pipe_config->base.adjusted_mode;

		&pipe_config->hw.adjusted_mode;



	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)

		return -EINVAL;

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