Commit 1325b655 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'spi-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 

Pull spi updates from Mark Brown:
 "A quiet release, more bug fixes than anything else.  A few things do
  stand out though:

   - updates to several drivers to move towards the standard GPIO chip
     select handling in the core.
   - DMA support for the SH MSIOF driver.
   - support for Rockchip SPI controllers (their first mainline
     submission)"

* tag 'spi-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (64 commits)
  spi: davinci: use spi_device.cs_gpio to store gpio cs per spi device
  spi: davinci: add support to configure gpio cs through dt
  spi/pl022: Explicitly truncate large bitmask
  spi/atmel: Fix pointer to int conversion warnings on 64 bit builds
  spi: davinci: fix to support more than 2 chip selects
  spi: topcliff-pch: don't hardcode PCI slot to get DMA device
  spi: orion: fix incorrect handling of cell-index DT property
  spi: orion: Fix error return code in orion_spi_probe()
  spi/rockchip: fix error return code in rockchip_spi_probe()
  spi/rockchip: remove redundant dev_err call in rockchip_spi_probe()
  spi/rockchip: remove duplicated include from spi-rockchip.c
  ARM: dts: fix the chip select gpios definition in the SPI nodes
  spi: s3c64xx: Update binding documentation
  spi: s3c64xx: use the generic SPI "cs-gpios" property
  spi: s3c64xx: Revert "spi: s3c64xx: Added provision for dedicated cs pin"
  spi: atmel: Use dmaengine_prep_slave_sg() API
  spi: topcliff-pch: Update error messages for dmaengine_prep_slave_sg() API
  spi: sh-msiof: Use correct device for DMA mapping with IOMMU
  spi: sh-msiof: Handle dmaengine_prep_slave_single() failures gracefully
  spi: rspi: Handle dmaengine_prep_slave_sg() failures gracefully
  ...
parents dc7aafba fab6a041

Documentation/devicetree/bindings/spi/efm32-spi.txt

+7 −6
Original line number Diff line number Diff line
@@ -10,11 +10,12 @@ Required properties: 
- cs-gpios: see spi-bus.txt



Recommended properties :

- efm32,location: Value to write to the ROUTE register's LOCATION bitfield to

                  configure the pinmux for the device, see datasheet for values.

                  If "efm32,location" property is not provided, keeping what is

                  already configured in the hardware, so its either the reset

                  default 0 or whatever the bootloader did.

- energymicro,location: Value to write to the ROUTE register's LOCATION

                        bitfield to configure the pinmux for the device, see

                        datasheet for values.

                        If this property is not provided, keeping what is

                        already configured in the hardware, so its either the

                        reset default 0 or whatever the bootloader did.



Example:
@@ -26,7 +27,7 @@ spi1: spi@0x4000c400 { /* USART1 */ 
	interrupts = <15 16>;

	clocks = <&cmu 20>;

	cs-gpios = <&gpio 51 1>; // D3

	efm32,location = <1>;

	energymicro,location = <1>;

	status = "ok";



	ks8851@0 {

Documentation/devicetree/bindings/spi/qcom,spi-qup.txt

+5 −1
Original line number Diff line number Diff line
@@ -7,7 +7,11 @@ SPI in master mode supports up to 50MHz, up to four chip selects, programmable 
data path from 4 bits to 32 bits and numerous protocol variants.



Required properties:

- compatible:     Should contain "qcom,spi-qup-v2.1.1" or "qcom,spi-qup-v2.2.1"

- compatible:     Should contain:

		  "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.

		  "qcom,spi-qup-v2.1.1" for 8974 and later

		  "qcom,spi-qup-v2.2.1" for 8974 v2 and later.



- reg:            Should contain base register location and length

- interrupts:     Interrupt number used by this controller

Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt

0 → 100644
+28 −0
Original line number Diff line number Diff line 
Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.



Required properties:

- compatible : "snps,dw-apb-ssi"

- reg : The register base for the controller.

- interrupts : One interrupt, used by the controller.

- #address-cells : <1>, as required by generic SPI binding.

- #size-cells : <0>, also as required by generic SPI binding.



Optional properties:

- cs-gpios : Specifies the gpio pis to be used for chipselects.

- num-cs : The number of chipselects. If omitted, this will default to 4.



Child nodes as per the generic SPI binding.



Example:



	spi@fff00000 {

		compatible = "snps,dw-apb-ssi";

		reg = <0xfff00000 0x1000>;

		interrupts = <0 154 4>;

		#address-cells = <1>;

		#size-cells = <0>;

		num-cs = <2>;

		cs-gpios = <&gpio0 13 0>,

			   <&gpio0 14 0>;

	};

Documentation/devicetree/bindings/spi/spi-davinci.txt

+8 −1
Original line number Diff line number Diff line
@@ -8,7 +8,8 @@ Required properties: 
	- "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family

	- "ti,da830-spi" for SPI used similar to that on DA8xx SoC family

- reg: Offset and length of SPI controller register space

- num-cs: Number of chip selects

- num-cs: Number of chip selects. This includes internal as well as

	GPIO chip selects.

- ti,davinci-spi-intr-line: interrupt line used to connect the SPI

	IP to the interrupt controller within the SoC. Possible values

	are 0 and 1. Manual says one of the two possible interrupt
@@ -17,6 +18,12 @@ Required properties: 
- interrupts: interrupt number mapped to CPU.

- clocks: spi clk phandle



Optional:

- cs-gpios: gpio chip selects

	For example to have 3 internal CS and 2 GPIO CS, user could define

	cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>;

	where first three are internal CS and last two are GPIO CS.



Example of a NOR flash slave device (n25q032) connected to DaVinci

SPI controller device over the SPI bus.

Documentation/devicetree/bindings/spi/spi-rockchip.txt

0 → 100644
+37 −0
Original line number Diff line number Diff line 
* Rockchip SPI Controller



The Rockchip SPI controller is used to interface with various devices such as flash

and display controllers using the SPI communication interface.



Required Properties:



- compatible: should be one of the following.

    "rockchip,rk3066-spi" for rk3066.

    "rockchip,rk3188-spi", "rockchip,rk3066-spi" for rk3188.

    "rockchip,rk3288-spi", "rockchip,rk3066-spi" for rk3288.

- reg: physical base address of the controller and length of memory mapped

       region.

- interrupts: The interrupt number to the cpu. The interrupt specifier format

              depends on the interrupt controller.

- clocks: Must contain an entry for each entry in clock-names.

- clock-names: Shall be "spiclk" for the transfer-clock, and "apb_pclk" for

			   the peripheral clock.

- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,

		Documentation/devicetree/bindings/dma/dma.txt

- dma-names: DMA request names should include "tx" and "rx" if present.

- #address-cells: should be 1.

- #size-cells: should be 0.



Example:



	spi0: spi@ff110000 {

		compatible = "rockchip,rk3066-spi";

		reg = <0xff110000 0x1000>;

		dmas = <&pdma1 11>, <&pdma1 12>;

		dma-names = "tx", "rx";

		#address-cells = <1>;

		#size-cells = <0>;

		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;

		clock-names = "spiclk", "apb_pclk";

	};

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