Commit 12fdafb8 authored by Meir Lichtinger's avatar Meir Lichtinger Committed by David S. Miller
Browse files

net/mlx5: Added support for 100Gbps per lane link modes 



This patch exposes new link modes using 100Gbps per lane, including 100G,
200G and 400G modes.

Signed-off-by: default avatarMeir Lichtinger <meirl@mellanox.com>
Reviewed-by: default avatarAya Levin <ayal@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 065e0d42

drivers/net/ethernet/mellanox/mlx5/core/en/port.c

+3 −0
Original line number Diff line number Diff line
@@ -76,6 +76,9 @@ static const u32 mlx5e_ext_link_speed[MLX5E_EXT_LINK_MODES_NUMBER] = { 
	[MLX5E_100GAUI_2_100GBASE_CR2_KR2]	= 100000,

	[MLX5E_200GAUI_4_200GBASE_CR4_KR4]	= 200000,

	[MLX5E_400GAUI_8]			= 400000,

	[MLX5E_100GAUI_1_100GBASE_CR_KR]	= 100000,

	[MLX5E_200GAUI_2_200GBASE_CR2_KR2]	= 200000,

	[MLX5E_400GAUI_4_400GBASE_CR4_KR4]	= 400000,

};



static void mlx5e_port_get_speed_arr(struct mlx5_core_dev *mdev,

drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c

+20 −1
Original line number Diff line number Diff line
@@ -194,6 +194,24 @@ void mlx5e_build_ptys2ethtool_map(void) 
				       ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,

				       ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,

				       ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);

	MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_1_100GBASE_CR_KR, ext,

				       ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,

				       ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,

				       ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT,

				       ETHTOOL_LINK_MODE_100000baseDR_Full_BIT,

				       ETHTOOL_LINK_MODE_100000baseCR_Full_BIT);

	MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_2_200GBASE_CR2_KR2, ext,

				       ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT,

				       ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT,

				       ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT,

				       ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT,

				       ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT);

	MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_4_400GBASE_CR4_KR4, ext,

				       ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT,

				       ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT,

				       ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT,

				       ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT,

				       ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT);

}



static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev,
@@ -1012,7 +1030,8 @@ static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes) 
	unsigned long modes[2];



	for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) {

		if (*ptys2ext_ethtool_table[i].advertised == 0)

		if (ptys2ext_ethtool_table[i].advertised[0] == 0 &&

		    ptys2ext_ethtool_table[i].advertised[1] == 0)

			continue;

		memset(modes, 0, sizeof(modes));

		bitmap_and(modes, ptys2ext_ethtool_table[i].advertised,

include/linux/mlx5/port.h

+3 −0
Original line number Diff line number Diff line
@@ -104,8 +104,11 @@ enum mlx5e_ext_link_mode { 
	MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR	= 8,

	MLX5E_CAUI_4_100GBASE_CR4_KR4		= 9,

	MLX5E_100GAUI_2_100GBASE_CR2_KR2	= 10,

	MLX5E_100GAUI_1_100GBASE_CR_KR		= 11,

	MLX5E_200GAUI_4_200GBASE_CR4_KR4	= 12,

	MLX5E_200GAUI_2_200GBASE_CR2_KR2	= 13,

	MLX5E_400GAUI_8				= 15,

	MLX5E_400GAUI_4_400GBASE_CR4_KR4	= 16,

	MLX5E_EXT_LINK_MODES_NUMBER,

};

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