Unverified Commit 12dbb04f authored Oct 01, 2019 by Paul Burton

MIPS: genex: Add Loongson3 LL/SC workaround to ejtag_debug_handler

In ejtag_debug_handler we use LL & SC instructions to acquire & release
an open-coded spinlock. For Loongson3 systems affected by LL/SC errata
this requires that we insert a sync instruction prior to the LL in order
to ensure correct behavior of the LL/SC loop.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: linux-kernel@vger.kernel.org

parent ae4cd0b1

arch/mips/kernel/genex.S

+2 −0

Original line number	Diff line number	Diff line
		@@ -18,6 +18,7 @@
		#include <asm/fpregdef.h>
		#include <asm/mipsregs.h>
		#include <asm/stackframe.h>
		#include <asm/sync.h>
		#include <asm/war.h>
		#include <asm/thread_info.h>

		@@ -353,6 +354,7 @@ NESTED(ejtag_debug_handler, PT_SIZE, sp)

		#ifdef CONFIG_SMP
		1: PTR_LA k0, ejtag_debug_buffer_spinlock
		__SYNC(full, loongson3_war)
		ll k0, 0(k0)
		bnez k0, 1b
		PTR_LA k0, ejtag_debug_buffer_spinlock

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