Commit 12d58619 authored by Pankaj Bharadiya's avatar Pankaj Bharadiya Committed by Zhenyu Wang
Browse files

drm/i915/gvt: Make WARN* drm specific where vgpu ptr is available 



Drm specific drm_WARN* calls include device information in the
backtrace, so we know what device the warnings originate from.

Covert all the calls of WARN* with device specific drm_WARN*
variants in functions where drm_device struct pointer is readily
available.

The conversion was done automatically with below coccinelle semantic
patch. checkpatch errors/warnings are fixed manually.

@@
identifier func, T;
@@
func(struct intel_vgpu *T,...) {
+struct drm_i915_private *i915 = T->gvt->dev_priv;
<+...
(
-WARN(
+drm_WARN(&i915->drm,
...)
|
-WARN_ON(
+drm_WARN_ON(&i915->drm,
...)
|
-WARN_ONCE(
+drm_WARN_ONCE(&i915->drm,
...)
|
-WARN_ON_ONCE(
+drm_WARN_ON_ONCE(&i915->drm,
...)
)
...+>

}

Signed-off-by: default avatarPankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Acked-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20200220165507.16823-9-pankaj.laxminarayan.bharadiya@intel.com
parent db19c724

drivers/gpu/drm/i915/gvt/cfg_space.c

+14 −9
Original line number Diff line number Diff line
@@ -106,10 +106,13 @@ static void vgpu_pci_cfg_mem_write(struct intel_vgpu *vgpu, unsigned int off, 
int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,

	void *p_data, unsigned int bytes)

{

	if (WARN_ON(bytes > 4))

	struct drm_i915_private *i915 = vgpu->gvt->dev_priv;



	if (drm_WARN_ON(&i915->drm, bytes > 4))

		return -EINVAL;



	if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size))

	if (drm_WARN_ON(&i915->drm,

			offset + bytes > vgpu->gvt->device_info.cfg_space_size))

		return -EINVAL;



	memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes);
@@ -297,34 +300,36 @@ static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset, 
int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,

	void *p_data, unsigned int bytes)

{

	struct drm_i915_private *i915 = vgpu->gvt->dev_priv;

	int ret;



	if (WARN_ON(bytes > 4))

	if (drm_WARN_ON(&i915->drm, bytes > 4))

		return -EINVAL;



	if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size))

	if (drm_WARN_ON(&i915->drm,

			offset + bytes > vgpu->gvt->device_info.cfg_space_size))

		return -EINVAL;



	/* First check if it's PCI_COMMAND */

	if (IS_ALIGNED(offset, 2) && offset == PCI_COMMAND) {

		if (WARN_ON(bytes > 2))

		if (drm_WARN_ON(&i915->drm, bytes > 2))

			return -EINVAL;

		return emulate_pci_command_write(vgpu, offset, p_data, bytes);

	}



	switch (rounddown(offset, 4)) {

	case PCI_ROM_ADDRESS:

		if (WARN_ON(!IS_ALIGNED(offset, 4)))

		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))

			return -EINVAL;

		return emulate_pci_rom_bar_write(vgpu, offset, p_data, bytes);



	case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5:

		if (WARN_ON(!IS_ALIGNED(offset, 4)))

		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))

			return -EINVAL;

		return emulate_pci_bar_write(vgpu, offset, p_data, bytes);



	case INTEL_GVT_PCI_SWSCI:

		if (WARN_ON(!IS_ALIGNED(offset, 4)))

		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))

			return -EINVAL;

		ret = intel_vgpu_emulate_opregion_request(vgpu, *(u32 *)p_data);

		if (ret)
@@ -332,7 +337,7 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 
		break;



	case INTEL_GVT_PCI_OPREGION:

		if (WARN_ON(!IS_ALIGNED(offset, 4)))

		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))

			return -EINVAL;

		ret = intel_vgpu_opregion_base_write_handler(vgpu,

						   *(u32 *)p_data);

drivers/gpu/drm/i915/gvt/display.c

+2 −1
Original line number Diff line number Diff line
@@ -320,9 +320,10 @@ static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) 
static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,

				    int type, unsigned int resolution)

{

	struct drm_i915_private *i915 = vgpu->gvt->dev_priv;

	struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);



	if (WARN_ON(resolution >= GVT_EDID_NUM))

	if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM))

		return -EINVAL;



	port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);

drivers/gpu/drm/i915/gvt/edid.c

+12 −5
Original line number Diff line number Diff line
@@ -276,7 +276,9 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 
static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,

	void *p_data, unsigned int bytes)

{

	WARN_ON(1);

	struct drm_i915_private *i915 = vgpu->gvt->dev_priv;



	drm_WARN_ON(&i915->drm, 1);

	return 0;

}
@@ -371,7 +373,9 @@ static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 
int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,

	unsigned int offset, void *p_data, unsigned int bytes)

{

	if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))

	struct drm_i915_private *i915 = vgpu->gvt->dev_priv;



	if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))

		return -EINVAL;



	if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
@@ -399,7 +403,9 @@ int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu, 
int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,

		unsigned int offset, void *p_data, unsigned int bytes)

{

	if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))

	struct drm_i915_private *i915 = vgpu->gvt->dev_priv;



	if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))

		return -EINVAL;



	if (offset == i915_mmio_reg_offset(PCH_GMBUS0))
@@ -473,6 +479,7 @@ void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu, 
				unsigned int offset,

				void *p_data)

{

	struct drm_i915_private *i915 = vgpu->gvt->dev_priv;

	struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;

	int msg_length, ret_msg_size;

	int msg, addr, ctrl, op;
@@ -532,9 +539,9 @@ void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu, 
		 * support the gfx driver to do EDID access.

		 */

	} else {

		if (WARN_ON((op & 0x1) != GVT_AUX_I2C_READ))

		if (drm_WARN_ON(&i915->drm, (op & 0x1) != GVT_AUX_I2C_READ))

			return;

		if (WARN_ON(msg_length != 4))

		if (drm_WARN_ON(&i915->drm, msg_length != 4))

			return;

		if (i2c_edid->edid_available && i2c_edid->slave_selected) {

			unsigned char val = edid_get_byte(vgpu);

drivers/gpu/drm/i915/gvt/gtt.c

+15 −6
Original line number Diff line number Diff line
@@ -71,7 +71,9 @@ bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size) 
/* translate a guest gmadr to host gmadr */

int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr)

{

	if (WARN(!vgpu_gmadr_is_valid(vgpu, g_addr),

	struct drm_i915_private *i915 = vgpu->gvt->dev_priv;



	if (drm_WARN(&i915->drm, !vgpu_gmadr_is_valid(vgpu, g_addr),

		     "invalid guest gmadr %llx\n", g_addr))

		return -EACCES;
@@ -87,7 +89,9 @@ int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr) 
/* translate a host gmadr to guest gmadr */

int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr)

{

	if (WARN(!gvt_gmadr_is_valid(vgpu->gvt, h_addr),

	struct drm_i915_private *i915 = vgpu->gvt->dev_priv;



	if (drm_WARN(&i915->drm, !gvt_gmadr_is_valid(vgpu->gvt, h_addr),

		     "invalid host gmadr %llx\n", h_addr))

		return -EACCES;
@@ -940,6 +944,7 @@ static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt); 
static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,

		struct intel_gvt_gtt_entry *e)

{

	struct drm_i915_private *i915 = vgpu->gvt->dev_priv;

	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;

	struct intel_vgpu_ppgtt_spt *s;

	enum intel_gvt_gtt_type cur_pt_type;
@@ -952,7 +957,9 @@ static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu, 


		if (!gtt_type_is_pt(cur_pt_type) ||

				!gtt_type_is_pt(cur_pt_type + 1)) {

			WARN(1, "Invalid page table type, cur_pt_type is: %d\n", cur_pt_type);

			drm_WARN(&i915->drm, 1,

				 "Invalid page table type, cur_pt_type is: %d\n",

				 cur_pt_type);

			return -EINVAL;

		}
@@ -2343,6 +2350,7 @@ int intel_vgpu_emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, 
static int alloc_scratch_pages(struct intel_vgpu *vgpu,

		enum intel_gvt_gtt_type type)

{

	struct drm_i915_private *i915 = vgpu->gvt->dev_priv;

	struct intel_vgpu_gtt *gtt = &vgpu->gtt;

	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;

	int page_entry_num = I915_GTT_PAGE_SIZE >>
@@ -2352,7 +2360,8 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu, 
	struct device *dev = &vgpu->gvt->dev_priv->drm.pdev->dev;

	dma_addr_t daddr;



	if (WARN_ON(type < GTT_TYPE_PPGTT_PTE_PT || type >= GTT_TYPE_MAX))

	if (drm_WARN_ON(&i915->drm,

			type < GTT_TYPE_PPGTT_PTE_PT || type >= GTT_TYPE_MAX))

		return -EINVAL;



	scratch_pt = (void *)get_zeroed_page(GFP_KERNEL);

drivers/gpu/drm/i915/gvt/handlers.c

+14 −6
Original line number Diff line number Diff line
@@ -1306,12 +1306,14 @@ static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 
static int pf_write(struct intel_vgpu *vgpu,

		unsigned int offset, void *p_data, unsigned int bytes)

{

	struct drm_i915_private *i915 = vgpu->gvt->dev_priv;

	u32 val = *(u32 *)p_data;



	if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||

	   offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||

	   offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {

		WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n",

		drm_WARN_ONCE(&i915->drm, true,

			      "VM(%d): guest is trying to scaling a plane\n",

			      vgpu->id);

		return 0;

	}
@@ -1360,13 +1362,15 @@ static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 
static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,

		void *p_data, unsigned int bytes)

{

	struct drm_i915_private *i915 = vgpu->gvt->dev_priv;

	u32 mode;



	write_vreg(vgpu, offset, p_data, bytes);

	mode = vgpu_vreg(vgpu, offset);



	if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {

		WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n",

		drm_WARN_ONCE(&i915->drm, 1,

				"VM(%d): iGVT-g doesn't support GuC\n",

				vgpu->id);

		return 0;

	}
@@ -1377,10 +1381,12 @@ static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 
static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,

		void *p_data, unsigned int bytes)

{

	struct drm_i915_private *i915 = vgpu->gvt->dev_priv;

	u32 trtte = *(u32 *)p_data;



	if ((trtte & 1) && (trtte & (1 << 1)) == 0) {

		WARN(1, "VM(%d): Use physical address for TRTT!\n",

		drm_WARN(&i915->drm, 1,

				"VM(%d): Use physical address for TRTT!\n",

				vgpu->id);

		return -EINVAL;

	}
@@ -1682,12 +1688,13 @@ static int mmio_read_from_hw(struct intel_vgpu *vgpu, 
static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,

		void *p_data, unsigned int bytes)

{

	struct drm_i915_private *i915 = vgpu->gvt->dev_priv;

	int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);

	struct intel_vgpu_execlist *execlist;

	u32 data = *(u32 *)p_data;

	int ret = 0;



	if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES))

	if (drm_WARN_ON(&i915->drm, ring_id < 0 || ring_id >= I915_NUM_ENGINES))

		return -EINVAL;



	execlist = &vgpu->submission.execlist[ring_id];
@@ -3541,13 +3548,14 @@ bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, 
int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,

			   void *pdata, unsigned int bytes, bool is_read)

{

	struct drm_i915_private *i915 = vgpu->gvt->dev_priv;

	struct intel_gvt *gvt = vgpu->gvt;

	struct intel_gvt_mmio_info *mmio_info;

	struct gvt_mmio_block *mmio_block;

	gvt_mmio_func func;

	int ret;



	if (WARN_ON(bytes > 8))

	if (drm_WARN_ON(&i915->drm, bytes > 8))

		return -EINVAL;



	/*

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