dt-bindings: mmc: arasan: Document 'xlnx,zynqmp-8.9a' controller (1297eacf) · Commits · 戴 / test

Documentation/devicetree/bindings/mmc/arasan,sdhci.txt

+19 −0

Original line number	Diff line number	Diff line
		@@ -15,6 +15,9 @@ Required Properties:
		- "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
		- "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
		For this device it is strongly suggested to include arasan,soc-ctl-syscon.
		- "xlnx,zynqmp-8.9a": ZynqMP SDHCI 8.9a PHY
		For this device it is strongly suggested to include clock-output-names and
		#clock-cells.
		- "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY
		Note: This binding has been deprecated and moved to [5].
		- "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY
		@@ -49,6 +52,10 @@ Optional Properties:
		- xlnx,int-clock-stable-broken: when present, the controller always reports
		that the internal clock is stable even when it is not.

		- xlnx,mio-bank: When specified, this will indicate the MIO bank number in
		which the command and data lines are configured. If not specified, driver
		will assume this as 0.

		Example:
		sdhci@e0100000 {
		compatible = "arasan,sdhci-8.9a";
		@@ -85,6 +92,18 @@ Example:
		#clock-cells = <0>;
		};

		sdhci: mmc@ff160000 {
		compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
		interrupt-parent = <&gic>;
		interrupts = <0 48 4>;
		reg = <0x0 0xff160000 0x0 0x1000>;
		clocks = <&clk200>, <&clk200>;
		clock-names = "clk_xin", "clk_ahb";
		clock-output-names = "clk_out_sd0", "clk_in_sd0";
		#clock-cells = <1>;
		clk-phase-sd-hs = <63>, <72>;
		};

		emmc: sdhci@ec700000 {
		compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
		reg = <0xec700000 0x300>;