[ARM] 3894/1: pxa27x: Update DCSR_EORINTR bit definition in DCSR (127e477e) · Commits · 戴 / test

This patch updates a bit definition name to align with the PXA27x spec.EORINTR(End-Of-Receive Intr) bit in DCSR register (DMA Channel Control/Status Register) Signed-off-by:

Stanley Cai <stanley.w.cai@gmail.com> Signed-off-by:

Russell King <rmk+kernel@arm.linux.org.uk>

include/asm-arm/arch-pxa/pxa-regs.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -99,7 +99,7 @@
		#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
		#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
		#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
		#define DCSR_ENRINTR (1 << 9) /* The end of Receive */
		#define DCSR_EORINTR (1 << 9) /* The end of Receive */
		#endif
		#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
		#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */

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