e1000: updated whitespace and comments

#include "e1000_osdep.h"

/* Forward declarations of structures used by the shared code */

struct e1000_hw;

struct e1000_hw_stats;

	e1000_dword_align = 2

} e1000_align_type;

/* Error Codes */

#define E1000_SUCCESS      0

#define E1000_ERR_EEPROM   1

/* Everything else */

void e1000_reset_adaptive(struct e1000_hw *hw);

void e1000_update_adaptive(struct e1000_hw *hw);

void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, u32 frame_len, u8 * mac_addr);

void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,

			    u32 frame_len, u8 * mac_addr);

void e1000_get_bus_info(struct e1000_hw *hw);

void e1000_pci_set_mwi(struct e1000_hw *hw);

void e1000_pci_clear_mwi(struct e1000_hw *hw);

/* Port I/O is only supported on 82544 and newer */

void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);

#define E1000_READ_REG_IO(a, reg) \

    e1000_read_reg_io((a), E1000_##reg)

#define E1000_WRITE_REG_IO(a, reg, val) \

#define CRC_LENGTH                   ETHERNET_FCS_SIZE

#define MAX_JUMBO_FRAME_SIZE         0x3F00

/* 802.1q VLAN Packet Sizes */

#define VLAN_TAG_SIZE  4	/* 802.3ac tag (not DMAed) */

	} wb;			/* writeback */

};

/* Receive Decriptor bit definitions */

/* Receive Descriptor bit definitions */

#define E1000_RXD_STAT_DD       0x01	/* Descriptor Done */

#define E1000_RXD_STAT_EOP      0x02	/* End of Packet */

#define E1000_RXD_STAT_IXSM     0x04	/* Ignore checksum */

#define E1000_RXD_STAT_VP       0x08	/* IEEE VLAN Packet */

#define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum caculated */

#define E1000_RXD_STAT_UDPCS    0x10	/* UDP xsum calculated */

#define E1000_RXD_STAT_TCPCS    0x20	/* TCP xsum calculated */

#define E1000_RXD_STAT_IPCS     0x40	/* IP xsum calculated */

#define E1000_RXD_STAT_PIF      0x80	/* passed in-exact filter */

    E1000_RXD_ERR_CXE |                \

    E1000_RXD_ERR_RXE)

/* Same mask, but for extended and packet split descriptors */

#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \

    E1000_RXDEXT_STATERR_CE  |            \

    E1000_RXDEXT_STATERR_CXE |            \

    E1000_RXDEXT_STATERR_RXE)

/* Transmit Descriptor */

struct e1000_tx_desc {

	__le64 buffer_addr;	/* Address of the descriptor's data buffer */

#define E1000_KUMCTRLSTA 0x00034	/* MAC-PHY interface - RW */

#define E1000_MDPHYA     0x0003C	/* PHY address - RW */

#define E1000_MANC2H     0x05860	/* Managment Control To Host - RW */

#define E1000_SW_FW_SYNC 0x05B5C	/* Software-Firmware Synchronization - RW */

#define E1000_GCR       0x05B00	/* PCI-Ex Control */

#define E1000_SWSM      0x05B50	/* SW Semaphore */

#define E1000_FWSM      0x05B54	/* FW Semaphore */

#define E1000_FFLT_DBG  0x05F04	/* Debug Register */

#define E1000_HICR      0x08F00 /* Host Inteface Control */

#define E1000_HICR      0x08F00	/* Host Interface Control */

/* RSS registers */

#define E1000_CPUVEC    0x02C10	/* CPU Vector Register - RW */

	bool has_smbus;

};

#define E1000_EEPROM_SWDPIN0   0x0001	/* SWDPIN 0 EEPROM Value */

#define E1000_EEPROM_LED_LOGIC 0x0020	/* Led Logic Word */

#define E1000_EEPROM_RW_REG_DATA   16	/* Offset to data in EEPROM read/write registers */

#define E1000_STATUS_SERDES0_DIS  0x10000000	/* SERDES disabled on port 0 */

#define E1000_STATUS_SERDES1_DIS  0x20000000	/* SERDES disabled on port 1 */

/* Constants used to intrepret the masked PCI-X bus speed. */

/* Constants used to interpret the masked PCI-X bus speed. */

#define E1000_STATUS_PCIX_SPEED_66  0x00000000	/* PCI-X bus speed  50-66 MHz */

#define E1000_STATUS_PCIX_SPEED_100 0x00004000	/* PCI-X bus speed  66-100 MHz */

#define E1000_STATUS_PCIX_SPEED_133 0x00008000	/* PCI-X bus speed 100-133 MHz */

#define E1000_ICR_ALL_PARITY    0x03F00000	/* all parity error bits */

#define E1000_ICR_DSW           0x00000020	/* FW changed the status of DISSW bit in the FWSM */

#define E1000_ICR_PHYINT        0x00001000	/* LAN connected device generates an interrupt */

#define E1000_ICR_EPRST         0x00100000 /* ME handware reset occurs */

#define E1000_ICR_EPRST         0x00100000	/* ME hardware reset occurs */

/* Interrupt Cause Set */

#define E1000_ICS_TXDW      E1000_ICR_TXDW	/* Transmit desc written back */

	e1000_mng_mode_host_interface_only

} e1000_mng_mode;

/* Host Inteface Control Register */

/* Host Interface Control Register */

#define E1000_HICR_EN           0x00000001	/* Enable Bit - RO */

#define E1000_HICR_C            0x00000002	/* Driver sets this bit when done

						 * to put command in RAM */

#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5	/* EEPROM write opcode */

#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7	/* EEPROM erase opcode */

#define EEPROM_EWEN_OPCODE_MICROWIRE  0x13	/* EEPROM erase/write enable */

#define EEPROM_EWDS_OPCODE_MICROWIRE  0x10 /* EEPROM erast/write disable */

#define EEPROM_EWDS_OPCODE_MICROWIRE  0x10	/* EEPROM erase/write disable */

/* EEPROM Commands - SPI */

#define EEPROM_MAX_RETRY_SPI        5000	/* Max wait of 5ms, for RDY signal */

#define IGP_ACTIVITY_LED_ENABLE 0x0300

#define IGP_LED3_MODE           0x07000000

/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */

#define EEPROM_SERDES_AMPLITUDE_MASK  0x000F

#define PCIX_STATUS_HI_MMRBC_4K      0x3

#define PCIX_STATUS_HI_MMRBC_2K      0x2

/* Number of bits required to shift right the "pause" bits from the

 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.

 */

 */

#define ILOS_SHIFT  3

#define RECEIVE_BUFFER_ALIGN_SIZE  (256)

/* Number of milliseconds we wait for auto-negotiation to complete */

          (((length) > (adapter)->min_frame_size) && \

           ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))

/* Structures, enums, and macros for the PHY */

/* Bit definitions for the Management Data IO (MDIO) and Management Data

/* PHY 1000 MII Register/Bit Definitions */

/* PHY Registers defined by IEEE */

#define PHY_CTRL         0x00	/* Control Register */

#define PHY_STATUS       0x01 /* Status Regiser */

#define PHY_STATUS       0x01	/* Status Register */

#define PHY_ID1          0x02	/* Phy Id Reg (word 1) */

#define PHY_ID2          0x03	/* Phy Id Reg (word 2) */

#define PHY_AUTONEG_ADV  0x04	/* Autoneg Advertisement */

#define M88E1111_I_PHY_ID  0x01410CC0

#define L1LXT971A_PHY_ID   0x001378E0

/* Bits...

 * 15-5: page

 * 4-0: register offset

#define IFE_PHY_EXTENDED_STATUS_CONTROL   0x10	/* 100BaseTx Extended Status, Control and Address */

#define IFE_PHY_SPECIAL_CONTROL           0x11	/* 100BaseTx PHY special control register */

#define IFE_PHY_RCV_FALSE_CARRIER         0x13	/* 100BaseTx Receive False Carrier Counter */

#define IFE_PHY_RCV_DISCONNECT            0x14  /* 100BaseTx Receive Disconnet Counter */

#define IFE_PHY_RCV_DISCONNECT            0x14	/* 100BaseTx Receive Disconnect Counter */

#define IFE_PHY_RCV_ERROT_FRAME           0x15	/* 100BaseTx Receive Error Frame Counter */

#define IFE_PHY_RCV_SYMBOL_ERR            0x16	/* Receive Symbol Error Counter */

#define IFE_PHY_PREM_EOF_ERR              0x17	/* 100BaseTx Receive Premature End Of Frame Error Counter */

#define IFE_PHY_MDIX_CONTROL              0x1C	/* MDI/MDI-X Control register */

#define IFE_PHY_HWI_CONTROL               0x1D	/* Hardware Integrity Control (HWI) */

#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE  0x2000  /* Defaut 1 = Disable auto reduced power down */

#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE  0x2000	/* Default 1 = Disable auto reduced power down */

#define IFE_PESC_100BTX_POWER_DOWN           0x0400	/* Indicates the power state of 100BASE-TX */

#define IFE_PESC_10BTX_POWER_DOWN            0x0200	/* Indicates the power state of 10BASE-T */

#define IFE_PESC_POLARITY_REVERSED           0x0100	/* Indicates 10BASE-T polarity */

#define IFE_PESC_DUPLEX                      0x0001	/* Auto-negotiation duplex result 1=Full, 0=Half */

#define IFE_PESC_POLARITY_REVERSED_SHIFT     8

#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN   0x0100  /* 1 = Dyanmic Power Down disabled */

#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN   0x0100	/* 1 = Dynamic Power Down disabled */

#define IFE_PSC_FORCE_POLARITY               0x0020	/* 1=Reversed Polarity, 0=Normal */

#define IFE_PSC_AUTO_POLARITY_DISABLE        0x0010	/* 1=Auto Polarity Disabled, 0=Enabled */

#define IFE_PSC_JABBER_FUNC_DISABLE          0x0001	/* 1=Jabber Disabled, 0=Normal Jabber Operation */

{

	struct e1000_hw *hw = &adapter->hw;

	bool link_active = false;

	s32 ret_val = 0;

	/* get_link_status is set on LSC (link status) interrupt or

	 * rx sequence error interrupt.  get_link_status will stay

	switch (hw->media_type) {

	case e1000_media_type_copper:

		if (hw->get_link_status) {

			ret_val = e1000_check_for_link(hw);

			e1000_check_for_link(hw);

			link_active = !hw->get_link_status;

		} else {

			link_active = true;

		}

		break;

	case e1000_media_type_fiber:

		ret_val = e1000_check_for_link(hw);

		e1000_check_for_link(hw);

		link_active = !!(er32(STATUS) & E1000_STATUS_LU);

		break;

	case e1000_media_type_internal_serdes:

		ret_val = e1000_check_for_link(hw);

		e1000_check_for_link(hw);

		link_active = hw->serdes_has_link;

		break;

	default:

		ew32(RCTL, rctl);

		if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {

			e1000_vlan_rx_kill_vid(netdev,

			                       adapter->mng_vlan_id);

			e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);

			adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;

		}

	}

/**

 * e1000_io_error_detected - called when PCI error is detected

 * @pdev: Pointer to PCI device

 * @state: The current pci conneection state

 * @state: The current pci connection state

 *

 * This function is called after a PCI bus error affecting

 * this device has been detected.