ARM: 7161/1: errata: no automatic store buffer drain (11ed0ba1) · Commits · 戴 / test

This patch implements a workaround for PL310 erratum 769419. On revisions of the PL310 prior to r3p2, the Store Buffer does not automatically drain. This can cause normal, non-cacheable writes to be retained when the memory system is idle, leading to suboptimal I/O performance for drivers using coherent DMA. This patch adds an optional wmb() call to the cpu_idle loop. On systems with an outer cache, this causes an explicit flush of the store buffer. Cc: stable@vger.kernel.org Acked-by:

Catalin Marinas <catalin.marinas@arm.com> Tested-by:

Marc Zyngier <marc.zyngier@arm.com> Signed-off-by:

Will Deacon <will.deacon@arm.com> Signed-off-by:

Russell King <rmk+kernel@arm.linux.org.uk>

arch/arm/Kconfig

+12 −0

Original line number	Diff line number	Diff line
		@@ -1352,6 +1352,18 @@ config ARM_ERRATA_764369
		relevant cache maintenance functions and sets a specific bit
		in the diagnostic control register of the SCU.

		config PL310_ERRATA_769419
		bool "PL310 errata: no automatic Store Buffer drain"
		depends on CACHE_L2X0
		help
		On revisions of the PL310 prior to r3p2, the Store Buffer does
		not automatically drain. This can cause normal, non-cacheable
		writes to be retained when the memory system is idle, leading
		to suboptimal I/O performance for drivers using coherent DMA.
		This option adds a write barrier to the cpu_idle loop so that,
		on systems with an outer cache, the store buffer is drained
		explicitly.

		endmenu

		source "arch/arm/common/Kconfig"

arch/arm/kernel/process.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -192,6 +192,9 @@ void cpu_idle(void)
		#endif

		local_irq_disable();
		#ifdef CONFIG_PL310_ERRATA_769419
		wmb();
		#endif
		if (hlt_counter) {
		local_irq_enable();
		cpu_relax();

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