Commit 11e54d35 authored by Haiyan Song's avatar Haiyan Song Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Add Tremontx event file v1.02 



Add a Intel event file for perf.

Signed-off-by: default avatarHaiyan Song <haiyanx.song@intel.com>
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Jin Yao <yao.jin@intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/20190815035942.30602-1-haiyanx.song@intel.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 4511708b

tools/perf/pmu-events/arch/x86/mapfile.csv

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@@ -35,4 +35,5 @@ GenuineIntel-6-55-[01234],v1,skylakex,core 
GenuineIntel-6-55-[56789ABCDEF],v1,cascadelakex,core

GenuineIntel-6-7D,v1,icelake,core

GenuineIntel-6-7E,v1,icelake,core

GenuineIntel-6-86,v1,tremontx,core

AuthenticAMD-23-[[:xdigit:]]+,v1,amdfam17h,core

tools/perf/pmu-events/arch/x86/tremontx/cache.json

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[

    {

        "CollectPEBSRecord": "2",

        "PublicDescription": "Counts cacheable memory requests that miss in the the Last Level Cache.  Requests include Demand Loads, Reads for Ownership(RFO), Instruction fetches and L1 HW prefetches. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2.",

        "EventCode": "0x2e",

        "Counter": "0,1,2,3",

        "UMask": "0x41",

        "PEBScounters": "0,1,2,3",

        "EventName": "LONGEST_LAT_CACHE.MISS",

        "PDIR_COUNTER": "na",

        "SampleAfterValue": "200003",

        "BriefDescription": "Counts memory requests originating from the core that miss in the last level cache. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2."

    },

    {

        "CollectPEBSRecord": "2",

        "PublicDescription": "Counts cacheable memory requests that access the Last Level Cache.  Requests include Demand Loads, Reads for Ownership(RFO), Instruction fetches and L1 HW prefetches. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2.",

        "EventCode": "0x2e",

        "Counter": "0,1,2,3",

        "UMask": "0x4f",

        "PEBScounters": "0,1,2,3",

        "EventName": "LONGEST_LAT_CACHE.REFERENCE",

        "PDIR_COUNTER": "na",

        "SampleAfterValue": "200003",

        "BriefDescription": "Counts memory requests originating from the core that reference a cache line in the last level cache. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2."

    },

    {

        "PEBS": "1",

        "CollectPEBSRecord": "2",

        "PublicDescription": "Counts the number of load uops retired. This event is Precise Event capable",

        "EventCode": "0xd0",

        "Counter": "0,1,2,3",

        "UMask": "0x81",

        "PEBScounters": "0,1,2,3",

        "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",

        "SampleAfterValue": "200003",

        "BriefDescription": "Counts the number of load uops retired.",

        "Data_LA": "1"

    },

    {

        "PEBS": "1",

        "CollectPEBSRecord": "2",

        "PublicDescription": "Counts the number of store uops retired. This event is Precise Event capable",

        "EventCode": "0xd0",

        "Counter": "0,1,2,3",

        "UMask": "0x82",

        "PEBScounters": "0,1,2,3",

        "EventName": "MEM_UOPS_RETIRED.ALL_STORES",

        "SampleAfterValue": "200003",

        "BriefDescription": "Counts the number of store uops retired.",

        "Data_LA": "1"

    },

    {

        "PEBS": "1",

        "CollectPEBSRecord": "2",

        "EventCode": "0xd1",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "PEBScounters": "0,1,2,3",

        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",

        "SampleAfterValue": "200003",

        "BriefDescription": "Counts the number of load uops retired that hit the level 1 data cache",

        "Data_LA": "1"

    },

    {

        "PEBS": "1",

        "CollectPEBSRecord": "2",

        "EventCode": "0xd1",

        "Counter": "0,1,2,3",

        "UMask": "0x2",

        "PEBScounters": "0,1,2,3",

        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",

        "SampleAfterValue": "200003",

        "BriefDescription": "Counts the number of load uops retired that hit in the level 2 cache",

        "Data_LA": "1"

    },

    {

        "PEBS": "1",

        "CollectPEBSRecord": "2",

        "EventCode": "0xd1",

        "Counter": "0,1,2,3",

        "UMask": "0x4",

        "PEBScounters": "0,1,2,3",

        "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",

        "SampleAfterValue": "200003",

        "BriefDescription": "Counts the number of load uops retired that miss in the level 3 cache"

    },

    {

        "PEBS": "1",

        "CollectPEBSRecord": "2",

        "EventCode": "0xd1",

        "Counter": "0,1,2,3",

        "UMask": "0x8",

        "PEBScounters": "0,1,2,3",

        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",

        "SampleAfterValue": "200003",

        "BriefDescription": "Counts the number of load uops retired that miss in the level 1 data cache",

        "Data_LA": "1"

    },

    {

        "PEBS": "1",

        "CollectPEBSRecord": "2",

        "EventCode": "0xd1",

        "Counter": "0,1,2,3",

        "UMask": "0x10",

        "PEBScounters": "0,1,2,3",

        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",

        "SampleAfterValue": "200003",

        "BriefDescription": "Counts the number of load uops retired that miss in the level 2 cache",

        "Data_LA": "1"

    }

]
 
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tools/perf/pmu-events/arch/x86/tremontx/frontend.json

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[

    {

        "CollectPEBSRecord": "2",

        "PublicDescription": "Counts requests to the Instruction Cache (ICache)  for one or more bytes in an ICache Line and that cache line is not in the ICache (miss).  The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS.  Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache.",

        "EventCode": "0x80",

        "Counter": "0,1,2,3",

        "UMask": "0x2",

        "PEBScounters": "0,1,2,3",

        "EventName": "ICACHE.MISSES",

        "PDIR_COUNTER": "na",

        "SampleAfterValue": "200003",

        "BriefDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in a cache line and they do not hit in the ICache (miss)."

    },

    {

        "CollectPEBSRecord": "2",

        "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line.  The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS.  Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.",

        "EventCode": "0x80",

        "Counter": "0,1,2,3",

        "UMask": "0x3",

        "PEBScounters": "0,1,2,3",

        "EventName": "ICACHE.ACCESSES",

        "PDIR_COUNTER": "na",

        "SampleAfterValue": "200003",

        "BriefDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes cache Line."

    }

]
 
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tools/perf/pmu-events/arch/x86/tremontx/memory.json

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[

    {

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "EventCode": "0XB7",

        "MSRValue": "0x000000003F04000001",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "SampleAfterValue": "100003",

        "BriefDescription": "Counts demand data reads that was not supplied by the L3 cache.",

        "Offcore": "1"

    },

    {

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "EventCode": "0XB7",

        "MSRValue": "0x000000003F04000002",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "EventName": "OCR.DEMAND_RFO.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "SampleAfterValue": "100003",

        "BriefDescription": "Counts all demand reads for ownership (RFO) requests and software based prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache.",

        "Offcore": "1"

    }

]
 
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tools/perf/pmu-events/arch/x86/tremontx/other.json

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[

    {

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "EventCode": "0XB7",

        "MSRValue": "0x000000000000010001",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",

        "SampleAfterValue": "100003",

        "BriefDescription": "Counts demand data reads that have any response type.",

        "Offcore": "1"

    },

    {

        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",

        "EventCode": "0XB7",

        "MSRValue": "0x000000000000010002",

        "Counter": "0,1,2,3",

        "UMask": "0x1",

        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",

        "SampleAfterValue": "100003",

        "BriefDescription": "Counts all demand reads for ownership (RFO) requests and software based prefetches for exclusive ownership (PREFETCHW) that have any response type.",

        "Offcore": "1"

    }

]
 
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