Commit 11e445e9 authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge tag 'perf-core-for-mingo-4.12-20170404' of... 

Merge tag 'perf-core-for-mingo-4.12-20170404' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux

 into perf/core

Pull perf/core improvements and fixes from Arnaldo Carvalho de Melo:

User visible changes:

- Add missing number of samples in 'perf annotate --stdio -l --show-total-period'
  (Taeung Song)

Vendor events updates:

- Add uncore_arb Intel vendor events in JSON format (Andi Kleen)

- Add uncore vendor events for Intel's Sandy Bridge, Ivy Bridge,
  Haswell, Broadwell and Skylake architectures (Andi Kleen)

- Add missing UNC_M_DCLOCKTICKS Intel Broadwell DE uncore vendor event (Andi Kleen)

Infrastructure changes:

- Remove some more die() calls, avoiding sudden death in library code
  (Arnaldo Carvalho de Melo)

- Add argument support for SDT events in powerpc (Ravi Bangoria)

Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parents fcc309e6 99094a5e

tools/perf/arch/powerpc/util/perf_regs.c

+111 −0
Original line number Diff line number Diff line 
#include <string.h>

#include <regex.h>



#include "../../perf.h"

#include "../../util/util.h"

#include "../../util/perf_regs.h"

#include "../../util/debug.h"



const struct sample_reg sample_reg_masks[] = {

	SMPL_REG(r0, PERF_REG_POWERPC_R0),
@@ -47,3 +52,109 @@ const struct sample_reg sample_reg_masks[] = { 
	SMPL_REG(dsisr, PERF_REG_POWERPC_DSISR),

	SMPL_REG_END

};



/* REG or %rREG */

#define SDT_OP_REGEX1  "^(%r)?([1-2]?[0-9]|3[0-1])$"



/* -NUM(REG) or NUM(REG) or -NUM(%rREG) or NUM(%rREG) */

#define SDT_OP_REGEX2  "^(\\-)?([0-9]+)\\((%r)?([1-2]?[0-9]|3[0-1])\\)$"



static regex_t sdt_op_regex1, sdt_op_regex2;



static int sdt_init_op_regex(void)

{

	static int initialized;

	int ret = 0;



	if (initialized)

		return 0;



	ret = regcomp(&sdt_op_regex1, SDT_OP_REGEX1, REG_EXTENDED);

	if (ret)

		goto error;



	ret = regcomp(&sdt_op_regex2, SDT_OP_REGEX2, REG_EXTENDED);

	if (ret)

		goto free_regex1;



	initialized = 1;

	return 0;



free_regex1:

	regfree(&sdt_op_regex1);

error:

	pr_debug4("Regex compilation error.\n");

	return ret;

}



/*

 * Parse OP and convert it into uprobe format, which is, +/-NUM(%gprREG).

 * Possible variants of OP are:

 *	Format		Example

 *	-------------------------

 *	NUM(REG)	48(18)

 *	-NUM(REG)	-48(18)

 *	NUM(%rREG)	48(%r18)

 *	-NUM(%rREG)	-48(%r18)

 *	REG		18

 *	%rREG		%r18

 *	iNUM		i0

 *	i-NUM		i-1

 *

 * SDT marker arguments on Powerpc uses %rREG form with -mregnames flag

 * and REG form with -mno-regnames. Here REG is general purpose register,

 * which is in 0 to 31 range.

 */

int arch_sdt_arg_parse_op(char *old_op, char **new_op)

{

	int ret, new_len;

	regmatch_t rm[5];

	char prefix;



	/* Constant argument. Uprobe does not support it */

	if (old_op[0] == 'i') {

		pr_debug4("Skipping unsupported SDT argument: %s\n", old_op);

		return SDT_ARG_SKIP;

	}



	ret = sdt_init_op_regex();

	if (ret < 0)

		return ret;



	if (!regexec(&sdt_op_regex1, old_op, 3, rm, 0)) {

		/* REG or %rREG --> %gprREG */



		new_len = 5;	/* % g p r NULL */

		new_len += (int)(rm[2].rm_eo - rm[2].rm_so);



		*new_op = zalloc(new_len);

		if (!*new_op)

			return -ENOMEM;



		scnprintf(*new_op, new_len, "%%gpr%.*s",

			(int)(rm[2].rm_eo - rm[2].rm_so), old_op + rm[2].rm_so);

	} else if (!regexec(&sdt_op_regex2, old_op, 5, rm, 0)) {

		/*

		 * -NUM(REG) or NUM(REG) or -NUM(%rREG) or NUM(%rREG) -->

		 *	+/-NUM(%gprREG)

		 */

		prefix = (rm[1].rm_so == -1) ? '+' : '-';



		new_len = 8;	/* +/- ( % g p r ) NULL */

		new_len += (int)(rm[2].rm_eo - rm[2].rm_so);

		new_len += (int)(rm[4].rm_eo - rm[4].rm_so);



		*new_op = zalloc(new_len);

		if (!*new_op)

			return -ENOMEM;



		scnprintf(*new_op, new_len, "%c%.*s(%%gpr%.*s)", prefix,

			(int)(rm[2].rm_eo - rm[2].rm_so), old_op + rm[2].rm_so,

			(int)(rm[4].rm_eo - rm[4].rm_so), old_op + rm[4].rm_so);

	} else {

		pr_debug4("Skipping unsupported SDT argument: %s\n", old_op);

		return SDT_ARG_SKIP;

	}



	return SDT_ARG_VALID;

}

tools/perf/perf.c

+2 −1
Original line number Diff line number Diff line
@@ -378,7 +378,8 @@ static void execv_dashed_external(const char **argv) 
	if (status != -ERR_RUN_COMMAND_EXEC) {

		if (IS_RUN_COMMAND_ERR(status)) {

do_die:

			die("unable to run '%s'", argv[0]);

			pr_err("FATAL: unable to run '%s'", argv[0]);

			status = -128;

		}

		exit(-status);

	}

tools/perf/pmu-events/arch/x86/broadwell/uncore.json

0 → 100644
+278 −0
Original line number Diff line number Diff line 
[

  {

    "Unit": "CBO",

    "EventCode": "0x22",

    "UMask": "0x41",

    "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE",

    "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",

    "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x22",

    "UMask": "0x81",

    "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",

    "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",

    "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x22",

    "UMask": "0x44",

    "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE",

    "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",

    "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x22",

    "UMask": "0x48",

    "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE",

    "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",

    "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x11",

    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",

    "BriefDescription": "L3 Lookup read request that access cache and found line in M-state",

    "PublicDescription": "L3 Lookup read request that access cache and found line in M-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x21",

    "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",

    "BriefDescription": "L3 Lookup write request that access cache and found line in M-state",

    "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x81",

    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M",

    "BriefDescription": "L3 Lookup any request that access cache and found line in M-state",

    "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x18",

    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I",

    "BriefDescription": "L3 Lookup read request that access cache and found line in I-state",

    "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x88",

    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I",

    "BriefDescription": "L3 Lookup any request that access cache and found line in I-state",

    "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x1f",

    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI",

    "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state",

    "PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x2f",

    "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI",

    "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state",

    "PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x8f",

    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI",

    "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state",

    "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x86",

    "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES",

    "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state",

    "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x16",

    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES",

    "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state",

    "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "CBO",

    "EventCode": "0x34",

    "UMask": "0x26",

    "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES",

    "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state",

    "PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "iMPH-U",

    "EventCode": "0x80",

    "UMask": "0x01",

    "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",

    "BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",

    "PublicDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",

    "Counter": "0,",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "iMPH-U",

    "EventCode": "0x80",

    "UMask": "0x02",

    "EventName": "UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT",

    "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",

    "PublicDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",

    "Counter": "0,",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "iMPH-U",

    "EventCode": "0x81",

    "UMask": "0x01",

    "EventName": "UNC_ARB_TRK_REQUESTS.ALL",

    "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",

    "PublicDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "iMPH-U",

    "EventCode": "0x81",

    "UMask": "0x02",

    "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT",

    "BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode",

    "PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "iMPH-U",

    "EventCode": "0x81",

    "UMask": "0x20",

    "EventName": "UNC_ARB_TRK_REQUESTS.WRITES",

    "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",

    "PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "iMPH-U",

    "EventCode": "0x84",

    "UMask": "0x01",

    "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL",

    "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",

    "PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.",

    "Counter": "0,1",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "iMPH-U",

    "EventCode": "0x80",

    "UMask": "0x01",

    "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",

    "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;",

    "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",

    "Counter": "0,",

    "CounterMask": "1",

    "Invert": "0",

    "EdgeDetect": "0"

  },

  {

    "Unit": "NCU",

    "EventCode": "0x0",

    "UMask": "0x01",

    "EventName": "UNC_CLOCK.SOCKET",

    "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles",

    "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",

    "Counter": "FIXED",

    "CounterMask": "0",

    "Invert": "0",

    "EdgeDetect": "0"

  }

]
 
 No newline at end of file

tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json

+10 −3
Original line number Diff line number Diff line
@@ -19,12 +19,19 @@ 
        "UMask": "0xC",

        "Unit": "iMC"

    },

    {

        "BriefDescription": "Memory controller clock ticks",

        "Counter": "0,1,2,3",

        "EventName": "UNC_M_DCLOCKTICKS",

        "PerPkg": "1",

        "Unit": "iMC"

    },

    {

        "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode",

        "Counter": "0,1,2,3",

        "EventCode": "0x85",

        "EventName": "UNC_M_POWER_CHANNEL_PPD",

        "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.",

        "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_DCLOCKTICKS) * 100.",

        "MetricName": "power_channel_ppd %",

        "PerPkg": "1",

        "Unit": "iMC"
@@ -34,7 +41,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x86",

        "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",

        "MetricExpr": "(UNC_M_POWER_CRITICAL_THROTTLE_CYCLES / UNC_M_CLOCKTICKS) * 100.",

        "MetricExpr": "(UNC_M_POWER_CRITICAL_THROTTLE_CYCLES / UNC_M_DCLOCKTICKS) * 100.",

        "MetricName": "power_critical_throttle_cycles %",

        "PerPkg": "1",

        "Unit": "iMC"
@@ -44,7 +51,7 @@ 
        "Counter": "0,1,2,3",

        "EventCode": "0x43",

        "EventName": "UNC_M_POWER_SELF_REFRESH",

        "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.",

        "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_DCLOCKTICKS) * 100.",

        "MetricName": "power_self_refresh %",

        "PerPkg": "1",

        "Unit": "iMC"

tools/perf/pmu-events/arch/x86/haswell/uncore.json

0 → 100644
+374 −0

File added.

Preview size limit exceeded, changes collapsed.

CRA Git | Maintained and supported by SUSTech CRA and CCSE