Commit 11d509ad authored Nov 23, 2018 by Alexandru Ardelean Committed by Jonathan Cameron Dec 01, 2018

staging:iio:ad2s90: Add max frequency check at probe

This patch adds a max frequency check at the beginning of ad2s90_probe
function so that when it is set to a value above 0.83Mhz, dev_err is
called with an appropriate message and -EINVAL is returned.

The defined limit is 0.83Mhz instead of 2Mhz, which is the chip's max
frequency as specified in the datasheet, because, as also specified in
the datasheet, a 600ns delay is expected between the application of a
logic LO to CS and the application of SCLK. Since the delay is not
implemented in the spi code, to satisfy it, SCLK's period should be at
most 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which
gives roughly 830000Hz.

Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Signed-off-by: Matheus Tavares <matheus.bernardino@usp.br>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

parent a996590b

drivers/staging/iio/resolver/ad2s90.c

+12 −0

Original line number	Diff line number	Diff line
		@@ -19,6 +19,12 @@
		#include <linux/iio/iio.h>
		#include <linux/iio/sysfs.h>

		/*
		* Although chip's max frequency is 2Mhz, it needs 600ns between CS and the
		* first falling edge of SCLK, so frequency should be at most 1 / (2 * 6e-7)
		*/
		#define AD2S90_MAX_SPI_FREQ_HZ 830000

		struct ad2s90_state {
		struct mutex lock;
		struct spi_device *sdev;
		@@ -78,6 +84,12 @@ static int ad2s90_probe(struct spi_device *spi)
		struct iio_dev *indio_dev;
		struct ad2s90_state *st;

		if (spi->max_speed_hz > AD2S90_MAX_SPI_FREQ_HZ) {
		dev_err(&spi->dev, "SPI CLK, %d Hz exceeds %d Hz\n",
		spi->max_speed_hz, AD2S90_MAX_SPI_FREQ_HZ);
		return -EINVAL;
		}

		indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
		if (!indio_dev)
		return -ENOMEM;

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