Commit 11c5ec78 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2020-04-23' of... 

Merge tag 'drm-intel-fixes-2020-04-23' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

- Tigerlake Workaround - disabling media recompression (Matt)
- Fix RPS interrupts for right GPU frequency (Chris)
- HDCP fix prime check (Oliver)
- Tigerlake Thunderbolt power well fix (Matt)
- Tigerlake DP link training fixes (Jose)
- Documentation sphinx build fix (Jani)
- Fix enable_dpcd_backlight modparam (Lyude)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200423190246.GA1710303@intel.com
parents c2c39adb d082119f

drivers/gpu/drm/i915/display/intel_ddi.c

+11 −3
Original line number Diff line number Diff line
@@ -3141,9 +3141,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder, 
	intel_dp_set_link_params(intel_dp, crtc_state->port_clock,

				 crtc_state->lane_count, is_mst);



	intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);

	intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);



	intel_edp_panel_on(intel_dp);



	intel_ddi_clk_select(encoder, crtc_state);
@@ -3848,12 +3845,18 @@ void intel_ddi_get_config(struct intel_encoder *encoder, 
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);

	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	u32 temp, flags = 0;



	/* XXX: DSI transcoder paranoia */

	if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))

		return;



	if (INTEL_GEN(dev_priv) >= 12) {

		intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(cpu_transcoder);

		intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(cpu_transcoder);

	}



	intel_dsc_get_config(encoder, pipe_config);



	temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
@@ -4173,6 +4176,7 @@ static const struct drm_encoder_funcs intel_ddi_funcs = { 
static struct intel_connector *

intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)

{

	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);

	struct intel_connector *connector;

	enum port port = intel_dig_port->base.port;
@@ -4183,6 +4187,10 @@ intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) 
	intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);

	intel_dig_port->dp.prepare_link_retrain =

		intel_ddi_prepare_link_retrain;

	if (INTEL_GEN(dev_priv) < 12) {

		intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);

		intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);

	}



	if (!intel_dp_init_connector(intel_dig_port, connector)) {

		kfree(connector);

drivers/gpu/drm/i915/display/intel_display_power.c

+6 −6
Original line number Diff line number Diff line
@@ -4140,7 +4140,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { 
	{

		.name = "AUX D TBT1",

		.domains = TGL_AUX_D_TBT1_IO_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.ops = &icl_tc_phy_aux_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,
@@ -4151,7 +4151,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { 
	{

		.name = "AUX E TBT2",

		.domains = TGL_AUX_E_TBT2_IO_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.ops = &icl_tc_phy_aux_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,
@@ -4162,7 +4162,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { 
	{

		.name = "AUX F TBT3",

		.domains = TGL_AUX_F_TBT3_IO_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.ops = &icl_tc_phy_aux_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,
@@ -4173,7 +4173,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { 
	{

		.name = "AUX G TBT4",

		.domains = TGL_AUX_G_TBT4_IO_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.ops = &icl_tc_phy_aux_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,
@@ -4184,7 +4184,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { 
	{

		.name = "AUX H TBT5",

		.domains = TGL_AUX_H_TBT5_IO_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.ops = &icl_tc_phy_aux_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,
@@ -4195,7 +4195,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { 
	{

		.name = "AUX I TBT6",

		.domains = TGL_AUX_I_TBT6_IO_POWER_DOMAINS,

		.ops = &hsw_power_well_ops,

		.ops = &icl_tc_phy_aux_power_well_ops,

		.id = DISP_PW_ID_NONE,

		{

			.hsw.regs = &icl_aux_power_well_regs,

drivers/gpu/drm/i915/display/intel_dp.c

+2 −3
Original line number Diff line number Diff line
@@ -2517,9 +2517,6 @@ static void intel_dp_prepare(struct intel_encoder *encoder, 
				 intel_crtc_has_type(pipe_config,

						     INTEL_OUTPUT_DP_MST));



	intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);

	intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);



	/*

	 * There are four kinds of DP registers:

	 *
@@ -7836,6 +7833,8 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, 


	intel_dig_port->dp.output_reg = output_reg;

	intel_dig_port->max_lanes = 4;

	intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);

	intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);



	intel_encoder->type = INTEL_OUTPUT_DP;

	intel_encoder->power_domain = intel_port_to_power_domain(port);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

+1 −0
Original line number Diff line number Diff line
@@ -342,6 +342,7 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector) 
	 */

	if (dev_priv->vbt.backlight.type !=

	    INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE &&

	    i915_modparams.enable_dpcd_backlight != 1 &&

	    !drm_dp_has_quirk(&intel_dp->desc, intel_dp->edid_quirks,

			      DP_QUIRK_FORCE_DPCD_BACKLIGHT)) {

		DRM_DEV_INFO(dev->dev,

drivers/gpu/drm/i915/display/intel_hdmi.c

+2 −1
Original line number Diff line number Diff line
@@ -1536,7 +1536,8 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) 
	intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);



	/* Wait for Ri prime match */

	if (wait_for(intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &

	if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &

		      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==

		     (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {

		DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",

			  intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)));

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