Commit 11964f53 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

Merge tag 'omap-devel-a2-for-3.7' of... 

Merge tag 'omap-devel-a2-for-3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into devel-am33xx

AM33xx hwmod data and miscellaneous clock and hwmod fixes.  AM33xx
should now boot on mainline after this is applied, according to
Vaibhav.

This second version includes trailing commas at the end of structure
records at Tony's request.  It also adds a OMAP_INTC_START macro
expansion to each IRQ number to make the sparseirq conversion easier.

Basic build, boot, and PM test transcripts are here:

http://www.pwsan.com/omap/testlogs/am33xx_hwmod_clock_devel_3.7/20120912165952/
parents 68cb700c 83c11542

arch/arm/mach-omap2/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -194,6 +194,7 @@ obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o 
obj-$(CONFIG_ARCH_OMAP3)		+= omap_hwmod_2xxx_3xxx_ipblock_data.o

obj-$(CONFIG_ARCH_OMAP3)		+= omap_hwmod_2xxx_3xxx_interconnect_data.o

obj-$(CONFIG_ARCH_OMAP3)		+= omap_hwmod_3xxx_data.o

obj-$(CONFIG_SOC_AM33XX)		+= omap_hwmod_33xx_data.o

obj-$(CONFIG_ARCH_OMAP4)		+= omap_hwmod_44xx_data.o



# EMU peripherals

arch/arm/mach-omap2/clkt_dpll.c

+2 −2
Original line number Diff line number Diff line
@@ -211,7 +211,7 @@ void omap2_init_dpll_parent(struct clk *clk) 
		if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||

		    v == OMAP3XXX_EN_DPLL_FRBYPASS)

			clk_reparent(clk, dd->clk_bypass);

	} else if (cpu_is_omap44xx()) {

	} else if (soc_is_am33xx() || cpu_is_omap44xx()) {

		if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||

		    v == OMAP4XXX_EN_DPLL_FRBYPASS ||

		    v == OMAP4XXX_EN_DPLL_MNBYPASS)
@@ -257,7 +257,7 @@ u32 omap2_get_dpll_rate(struct clk *clk) 
		if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||

		    v == OMAP3XXX_EN_DPLL_FRBYPASS)

			return dd->clk_bypass->rate;

	} else if (cpu_is_omap44xx()) {

	} else if (soc_is_am33xx() || cpu_is_omap44xx()) {

		if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||

		    v == OMAP4XXX_EN_DPLL_FRBYPASS ||

		    v == OMAP4XXX_EN_DPLL_MNBYPASS)

arch/arm/mach-omap2/clock33xx_data.c

+2 −0
Original line number Diff line number Diff line
@@ -1027,7 +1027,9 @@ static struct omap_clk am33xx_clks[] = { 
	CLK(NULL,	"cefuse_fck",		&cefuse_fck,	CK_AM33XX),

	CLK(NULL,	"clkdiv32k_ick",	&clkdiv32k_ick,	CK_AM33XX),

	CLK(NULL,	"dcan0_fck",		&dcan0_fck,	CK_AM33XX),

	CLK("481cc000.d_can",	NULL,		&dcan0_fck,	CK_AM33XX),

	CLK(NULL,	"dcan1_fck",		&dcan1_fck,	CK_AM33XX),

	CLK("481d0000.d_can",	NULL,		&dcan1_fck,	CK_AM33XX),

	CLK(NULL,	"debugss_ick",		&debugss_ick,	CK_AM33XX),

	CLK(NULL,	"pruss_ocp_gclk",	&pruss_ocp_gclk,	CK_AM33XX),

	CLK("davinci-mcasp.0",  NULL,           &mcasp0_fck,    CK_AM33XX),

arch/arm/mach-omap2/dpll3xxx.c

+2 −2
Original line number Diff line number Diff line
@@ -311,7 +311,7 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) 
	 * Set jitter correction. No jitter correction for OMAP4 and 3630

	 * since freqsel field is no longer present

	 */

	if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {

	if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {

		v = __raw_readl(dd->control_reg);

		v &= ~dd->freqsel_mask;

		v |= freqsel << __ffs(dd->freqsel_mask);
@@ -471,7 +471,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) 
			return -EINVAL;



		/* No freqsel on OMAP4 and OMAP3630 */

		if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {

		if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {

			freqsel = _omap3_dpll_compute_freqsel(clk,

						dd->last_rounded_n);

			if (!freqsel)

arch/arm/mach-omap2/io.c

+2 −0
Original line number Diff line number Diff line
@@ -524,6 +524,8 @@ void __init am33xx_init_early(void) 
	am33xx_voltagedomains_init();

	am33xx_powerdomains_init();

	am33xx_clockdomains_init();

	am33xx_hwmod_init();

	omap_hwmod_init_postsetup();

	am33xx_clk_init();

}

#endif

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