Unverified Commit 116edf6e authored by Quentin Schulz's avatar Quentin Schulz Committed by Paul Burton
Browse files

MIPS: mscc: add DT for Ocelot PCB120 



The Ocelot PCB120 evaluation board is different from the PCB123 in that
it has 4 external VSC8584 (or VSC8574) PHYs.

It uses the SoC's second MDIO bus for external PHYs which have a
reversed address on the bus (i.e. PHY4 is on address 3, PHY5 is on
address 2, PHY6 on 1 and PHY7 on 0).

Here is how the PHYs are connected to the switch ports:
port 0: phy0 (internal)
port 1: phy1 (internal)
port 2: phy2 (internal)
port 3: phy3 (internal)
port 4: phy7
port 5: phy4
port 6: phy6
port 9: phy5

Reviewed-by: default avatarAlexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: default avatarQuentin Schulz <quentin.schulz@bootlin.com>
Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20869/
Cc: ralf@linux-mips.org
Cc: jhogan@kernel.org
Cc: robh+dt@kernel.org
Cc: mark.rutland@arm.com
Cc: davem@davemloft.net
Cc: andrew@lunn.ch
Cc: f.fainelli@gmail.com
Cc: allan.nielsen@microchip.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: netdev@vger.kernel.org
Cc: thomas.petazzoni@bootlin.com
Cc: antoine.tenart@bootlin.com
parent 68dec269

arch/mips/boot/dts/mscc/Makefile

+1 −1
Original line number Diff line number Diff line 
dtb-$(CONFIG_MSCC_OCELOT)	+= ocelot_pcb123.dtb

dtb-$(CONFIG_MSCC_OCELOT)	+= ocelot_pcb123.dtb ocelot_pcb120.dtb



obj-$(CONFIG_BUILTIN_DTB)	+= $(addsuffix .o, $(dtb-y))

arch/mips/boot/dts/mscc/ocelot_pcb120.dts

0 → 100644
+107 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/* Copyright (c) 2017 Microsemi Corporation */



/dts-v1/;



#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/phy/phy-ocelot-serdes.h>

#include "ocelot.dtsi"



/ {

	compatible = "mscc,ocelot-pcb120", "mscc,ocelot";



	chosen {

		stdout-path = "serial0:115200n8";

	};



	memory@0 {

		device_type = "memory";

		reg = <0x0 0x0e000000>;

	};

};



&gpio {

	phy_int_pins: phy_int_pins {

		pins = "GPIO_4";

		function = "gpio";

	};

};



&mdio0 {

	status = "okay";

};



&mdio1 {

	status = "okay";

	pinctrl-names = "default";

	pinctrl-0 = <&miim1>, <&phy_int_pins>;



	phy7: ethernet-phy@0 {

		reg = <0>;

		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-parent = <&gpio>;

	};

	phy6: ethernet-phy@1 {

		reg = <1>;

		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-parent = <&gpio>;

	};

	phy5: ethernet-phy@2 {

		reg = <2>;

		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-parent = <&gpio>;

	};

	phy4: ethernet-phy@3 {

		reg = <3>;

		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-parent = <&gpio>;

	};

};



&port0 {

	phy-handle = <&phy0>;

};



&port1 {

	phy-handle = <&phy1>;

};



&port2 {

	phy-handle = <&phy2>;

};



&port3 {

	phy-handle = <&phy3>;

};



&port4 {

	phy-handle = <&phy7>;

	phy-mode = "sgmii";

	phys = <&serdes 4 SERDES1G(2)>;

};



&port5 {

	phy-handle = <&phy4>;

	phy-mode = "sgmii";

	phys = <&serdes 5 SERDES1G(5)>;

};



&port6 {

	phy-handle = <&phy6>;

	phy-mode = "sgmii";

	phys = <&serdes 6 SERDES1G(3)>;

};



&port9 {

	phy-handle = <&phy5>;

	phy-mode = "sgmii";

	phys = <&serdes 9 SERDES1G(4)>;

};



&uart0 {

	status = "okay";

};



&uart2 {

	status = "okay";

};

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