arm64: dts: renesas: initial V3HSK board device tree (116a12f7) · Commits · 戴 / test

arch/arm64/boot/dts/renesas/Makefile

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		@@ -9,6 +9,6 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
		dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
		dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
		dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
		dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb
		dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb r8a77980-v3hsk.dtb
		dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb
		dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb

0 → 100644

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		// SPDX-License-Identifier: GPL-2.0
		/*
		* Device Tree Source for the V3H Starter Kit board
		*
		* Copyright (C) 2018 Renesas Electronics Corp.
		* Copyright (C) 2018 Cogent Embedded, Inc.
		*/

		/dts-v1/;
		#include "r8a77980.dtsi"

		/ {
		model = "Renesas V3H Starter Kit board";
		compatible = "renesas,v3hsk", "renesas,r8a77980";

		aliases {
		serial0 = &scif0;
		};

		chosen {
		stdout-path = "serial0:115200n8";
		};

		memory@48000000 {
		device_type = "memory";
		/* first 128MB is reserved for secure area. */
		reg = <0 0x48000000 0 0x78000000>;
		};
		};

		&extal_clk {
		clock-frequency = <16666666>;
		};

		&extalr_clk {
		clock-frequency = <32768>;
		};

		&pfc {
		scif0_pins: scif0 {
		groups = "scif0_data";
		function = "scif0";
		};

		scif_clk_pins: scif_clk {
		groups = "scif_clk_b";
		function = "scif_clk";
		};
		};

		&scif0 {
		pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
		pinctrl-names = "default";

		status = "okay";
		};

		&scif_clk {
		clock-frequency = <14745600>;
		};