Commit 113a0476 authored by Brad Volkin's avatar Brad Volkin Committed by Daniel Vetter
Browse files

drm/i915: Add more registers to the whitelist for mesa 

These are additional registers needed for performance monitoring and
ARB_draw_indirect extensions in mesa.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76719


Cc: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: default avatarBrad Volkin <bradley.d.volkin@intel.com>
Reviewed-by: default avatarKenneth Graunke <kenneth@whitecape.org>
[danvet: Squash in fixup from Brad requested by Ken.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 932aae42

drivers/gpu/drm/i915/i915_cmd_parser.c

+10 −0
Original line number Diff line number Diff line
@@ -408,10 +408,20 @@ static const u32 gen7_render_regs[] = { 
	REG64(PS_INVOCATION_COUNT),

	REG64(PS_DEPTH_COUNT),

	OACONTROL, /* Only allowed for LRI and SRM. See below. */

	GEN7_3DPRIM_END_OFFSET,

	GEN7_3DPRIM_START_VERTEX,

	GEN7_3DPRIM_VERTEX_COUNT,

	GEN7_3DPRIM_INSTANCE_COUNT,

	GEN7_3DPRIM_START_INSTANCE,

	GEN7_3DPRIM_BASE_VERTEX,

	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)),

	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)),

	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)),

	REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)),

	REG64(GEN7_SO_PRIM_STORAGE_NEEDED(0)),

	REG64(GEN7_SO_PRIM_STORAGE_NEEDED(1)),

	REG64(GEN7_SO_PRIM_STORAGE_NEEDED(2)),

	REG64(GEN7_SO_PRIM_STORAGE_NEEDED(3)),

	GEN7_SO_WRITE_OFFSET(0),

	GEN7_SO_WRITE_OFFSET(1),

	GEN7_SO_WRITE_OFFSET(2),

drivers/gpu/drm/i915/i915_reg.h

+9 −0
Original line number Diff line number Diff line
@@ -428,6 +428,15 @@ 
/* There are the 4 64-bit counter registers, one for each stream output */

#define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)



#define GEN7_SO_PRIM_STORAGE_NEEDED(n)  (0x5240 + (n) * 8)



#define GEN7_3DPRIM_END_OFFSET          0x2420

#define GEN7_3DPRIM_START_VERTEX        0x2430

#define GEN7_3DPRIM_VERTEX_COUNT        0x2434

#define GEN7_3DPRIM_INSTANCE_COUNT      0x2438

#define GEN7_3DPRIM_START_INSTANCE      0x243C

#define GEN7_3DPRIM_BASE_VERTEX         0x2440



#define OACONTROL 0x2360



#define _GEN7_PIPEA_DE_LOAD_SL	0x70068

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