Commit 1137e1ea authored by Ofir Bitton's avatar Ofir Bitton Committed by Oded Gabbay
Browse files

habanalabs/gaudi: move coresight mmu config 



We must relocate the coresight mmu configuration to the coresight
flow to make it work in case the first submission is to configure
the profiler.

Signed-off-by: default avatarOfir Bitton <obitton@habana.ai>
Reviewed-by: default avatarOded Gabbay <ogabbay@kernel.org>
Signed-off-by: default avatarOded Gabbay <ogabbay@kernel.org>
parent 82948e6e

drivers/misc/habanalabs/gaudi/gaudi.c

+1 −4
Original line number Diff line number Diff line
@@ -4742,7 +4742,7 @@ static void gaudi_write_pte(struct hl_device *hdev, u64 addr, u64 val) 
			(addr - gaudi->hbm_bar_cur_addr));

}



static void gaudi_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid)

void gaudi_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid)

{

	/* mask to zero the MMBP and ASID bits */

	WREG32_AND(reg, ~0x7FF);
@@ -4910,9 +4910,6 @@ static void gaudi_mmu_prepare(struct hl_device *hdev, u32 asid) 
	gaudi_mmu_prepare_reg(hdev, mmMME2_ACC_WBC, asid);

	gaudi_mmu_prepare_reg(hdev, mmMME3_ACC_WBC, asid);



	gaudi_mmu_prepare_reg(hdev, mmPSOC_GLOBAL_CONF_TRACE_ARUSER, asid);

	gaudi_mmu_prepare_reg(hdev, mmPSOC_GLOBAL_CONF_TRACE_AWUSER, asid);



	hdev->asic_funcs->set_clock_gating(hdev);



	mutex_unlock(&gaudi->clk_gate_mutex);

drivers/misc/habanalabs/gaudi/gaudiP.h

+1 −0
Original line number Diff line number Diff line
@@ -271,5 +271,6 @@ void gaudi_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq); 
int gaudi_debug_coresight(struct hl_device *hdev, void *data);

void gaudi_halt_coresight(struct hl_device *hdev);

int gaudi_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk);

void gaudi_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid);



#endif /* GAUDIP_H_ */

drivers/misc/habanalabs/gaudi/gaudi_coresight.c

+5 −0
Original line number Diff line number Diff line
@@ -623,6 +623,11 @@ static int gaudi_config_etr(struct hl_device *hdev, 
			return -EINVAL;

		}



		gaudi_mmu_prepare_reg(hdev, mmPSOC_GLOBAL_CONF_TRACE_ARUSER,

						hdev->compute_ctx->asid);

		gaudi_mmu_prepare_reg(hdev, mmPSOC_GLOBAL_CONF_TRACE_AWUSER,

						hdev->compute_ctx->asid);



		msb = upper_32_bits(input->buffer_address) >> 8;

		msb &= PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK;

		WREG32(mmPSOC_GLOBAL_CONF_TRACE_ADDR, msb);

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