Commit 112c3523 authored by Peter Collingbourne's avatar Peter Collingbourne Committed by Daniel Vetter
Browse files

Partially revert "video: fbdev: amba-clcd: Retire elder CLCD driver" 



Also partially revert the follow-up change "drm: pl111: Absorb the
external register header".

This reverts the parts of commits
7e4e589d and
0fb81256 that touch paths outside
of drivers/gpu/drm/pl111.

The fbdev driver is used by Android's FVP configuration. Using the
DRM driver together with DRM's fbdev emulation results in a failure
to boot Android. The root cause is that Android's generic fbdev
userspace driver relies on the ability to set the pixel format via
FBIOPUT_VSCREENINFO, which is not supported by fbdev emulation.

There have been other less critical behavioral differences identified
between the fbdev driver and the DRM driver with fbdev emulation. The
DRM driver exposes different values for the panel's width, height and
refresh rate, and the DRM driver fails a FBIOPUT_VSCREENINFO syscall
with yres_virtual greater than the maximum supported value instead
of letting the syscall succeed and setting yres_virtual based on yres.

Signed-off-by: default avatarPeter Collingbourne <pcc@google.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20200929195344.2219796-1-pcc@google.com
parent 5af08640

MAINTAINERS

+5 −0
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@@ -1460,6 +1460,11 @@ S: Odd Fixes 
F:	drivers/amba/

F:	include/linux/amba/bus.h













ARM PRIMECELL CLCD PL110 DRIVER













M:	Russell King <linux@armlinux.org.uk>













S:	Odd Fixes













F:	drivers/video/fbdev/amba-clcd.*



























ARM PRIMECELL KMI PL050 DRIVER















M:	Russell King <linux@armlinux.org.uk>















S:	Odd Fixes

































drivers/video/fbdev/Kconfig



+20
−0






























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@@ -272,6 +272,26 @@ config FB_PM2_FIFO_DISCONNECT













	help















	  Support the Permedia2 FIFO disconnect feature.





























config FB_ARMCLCD













	tristate "ARM PrimeCell PL110 support"













	depends on ARM || ARM64 || COMPILE_TEST













	depends on FB && ARM_AMBA && HAS_IOMEM













	select FB_CFB_FILLRECT













	select FB_CFB_COPYAREA













	select FB_CFB_IMAGEBLIT













	select FB_MODE_HELPERS if OF













	select VIDEOMODE_HELPERS if OF













	select BACKLIGHT_CLASS_DEVICE if OF













	help













	  This framebuffer device driver is for the ARM PrimeCell PL110













	  Colour LCD controller.  ARM PrimeCells provide the building













	  blocks for System on a Chip devices.



























	  If you want to compile this as a module (=code which can be













	  inserted into and removed from the running kernel), say M













	  here and read <file:Documentation/kbuild/modules.rst>.  The module













	  will be called amba-clcd.





























config FB_ACORN















	bool "Acorn VIDC support"















	depends on (FB = y) && ARM && ARCH_ACORN

































drivers/video/fbdev/Makefile



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−0






























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@@ -75,6 +75,7 @@ obj-$(CONFIG_FB_HIT)              += hitfb.o













obj-$(CONFIG_FB_ATMEL)		  += atmel_lcdfb.o















obj-$(CONFIG_FB_PVR2)             += pvr2fb.o















obj-$(CONFIG_FB_VOODOO1)          += sstfb.o













obj-$(CONFIG_FB_ARMCLCD)	  += amba-clcd.o















obj-$(CONFIG_FB_GOLDFISH)         += goldfishfb.o















obj-$(CONFIG_FB_68328)            += 68328fb.o















obj-$(CONFIG_FB_GBE)              += gbefb.o

































drivers/video/fbdev/amba-clcd.c
0 → 100644



+986
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File added.
Preview size limit exceeded, changes collapsed.
























include/linux/amba/clcd-regs.h
0 → 100644



+87
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/*













 * David A Rusling













 *













 * Copyright (C) 2001 ARM Limited













 *













 * This file is subject to the terms and conditions of the GNU General Public













 * License.  See the file COPYING in the main directory of this archive













 * for more details.













 */



























#ifndef AMBA_CLCD_REGS_H













#define AMBA_CLCD_REGS_H



























/*













 * CLCD Controller Internal Register addresses













 */













#define CLCD_TIM0		0x00000000













#define CLCD_TIM1 		0x00000004













#define CLCD_TIM2 		0x00000008













#define CLCD_TIM3 		0x0000000c













#define CLCD_UBAS 		0x00000010













#define CLCD_LBAS 		0x00000014



























#define CLCD_PL110_IENB		0x00000018













#define CLCD_PL110_CNTL		0x0000001c













#define CLCD_PL110_STAT		0x00000020













#define CLCD_PL110_INTR 	0x00000024













#define CLCD_PL110_UCUR		0x00000028













#define CLCD_PL110_LCUR		0x0000002C



























#define CLCD_PL111_CNTL		0x00000018













#define CLCD_PL111_IENB		0x0000001c













#define CLCD_PL111_RIS		0x00000020













#define CLCD_PL111_MIS		0x00000024













#define CLCD_PL111_ICR		0x00000028













#define CLCD_PL111_UCUR		0x0000002c













#define CLCD_PL111_LCUR		0x00000030



























#define CLCD_PALL 		0x00000200













#define CLCD_PALETTE		0x00000200



























#define TIM2_PCD_LO_MASK	GENMASK(4, 0)













#define TIM2_PCD_LO_BITS	5













#define TIM2_CLKSEL		(1 << 5)













#define TIM2_ACB_MASK		GENMASK(10, 6)













#define TIM2_IVS		(1 << 11)













#define TIM2_IHS		(1 << 12)













#define TIM2_IPC		(1 << 13)













#define TIM2_IOE		(1 << 14)













#define TIM2_BCD		(1 << 26)













#define TIM2_PCD_HI_MASK	GENMASK(31, 27)













#define TIM2_PCD_HI_BITS	5













#define TIM2_PCD_HI_SHIFT	27



























#define CNTL_LCDEN		(1 << 0)













#define CNTL_LCDBPP1		(0 << 1)













#define CNTL_LCDBPP2		(1 << 1)













#define CNTL_LCDBPP4		(2 << 1)













#define CNTL_LCDBPP8		(3 << 1)













#define CNTL_LCDBPP16		(4 << 1)













#define CNTL_LCDBPP16_565	(6 << 1)













#define CNTL_LCDBPP16_444	(7 << 1)













#define CNTL_LCDBPP24		(5 << 1)













#define CNTL_LCDBW		(1 << 4)













#define CNTL_LCDTFT		(1 << 5)













#define CNTL_LCDMONO8		(1 << 6)













#define CNTL_LCDDUAL		(1 << 7)













#define CNTL_BGR		(1 << 8)













#define CNTL_BEBO		(1 << 9)













#define CNTL_BEPO		(1 << 10)













#define CNTL_LCDPWR		(1 << 11)













#define CNTL_LCDVCOMP(x)	((x) << 12)













#define CNTL_LDMAFIFOTIME	(1 << 15)













#define CNTL_WATERMARK		(1 << 16)



























/* ST Microelectronics variant bits */













#define CNTL_ST_1XBPP_444	0x0













#define CNTL_ST_1XBPP_5551	(1 << 17)













#define CNTL_ST_1XBPP_565	(1 << 18)













#define CNTL_ST_CDWID_12	0x0













#define CNTL_ST_CDWID_16	(1 << 19)













#define CNTL_ST_CDWID_18	(1 << 20)













#define CNTL_ST_CDWID_24	((1 << 19)|(1 << 20))













#define CNTL_ST_CEAEN		(1 << 21)













#define CNTL_ST_LCDBPP24_PACKED	(6 << 1)



























#endif /* AMBA_CLCD_REGS_H */
































































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