Commit 11179d8c authored by Catalin Marinas's avatar Catalin Marinas Committed by Russell King
Browse files

[ARM] 4497/1: Only allow safe cache configurations on ARMv6 and later 



Currently, Linux doesn't generate correct page tables for ARMv6 and
later cores if the cache policy is different from the default one (it
may lead to strongly ordered or shared device mappings). This patch
disallows cache policies other than writeback and the
CPU_[ID]CACHE_DISABLE options only affect the CP15 system control
register rather than the page tables.

Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 2eb8c82b

arch/arm/mm/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -599,7 +599,7 @@ config CPU_DCACHE_SIZE 


config CPU_DCACHE_WRITETHROUGH

	bool "Force write through D-cache"

	depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE

	depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE

	default y if CPU_ARM925T

	help

	  Say Y here to use the data cache in writethrough mode. Unless you

arch/arm/mm/mmu.c

+10 −4
Original line number Diff line number Diff line
@@ -114,6 +114,10 @@ static void __init early_cachepolicy(char **p) 
	}

	if (i == ARRAY_SIZE(cache_policies))

		printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");

	if (cpu_architecture() >= CPU_ARCH_ARMv6) {

		printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");

		cachepolicy = CPOLICY_WRITEBACK;

	}

	flush_cache_all();

	set_cr(cr_alignment);

}
@@ -252,6 +256,7 @@ static void __init build_mem_type_table(void) 
	int cpu_arch = cpu_architecture();

	int i;



	if (cpu_arch < CPU_ARCH_ARMv6) {

#if defined(CONFIG_CPU_DCACHE_DISABLE)

		if (cachepolicy > CPOLICY_BUFFERED)

			cachepolicy = CPOLICY_BUFFERED;
@@ -259,6 +264,7 @@ static void __init build_mem_type_table(void) 
		if (cachepolicy > CPOLICY_WRITETHROUGH)

			cachepolicy = CPOLICY_WRITETHROUGH;

#endif

	}

	if (cpu_arch < CPU_ARCH_ARMv5) {

		if (cachepolicy >= CPOLICY_WRITEALLOC)

			cachepolicy = CPOLICY_WRITEBACK;

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