Commit 1112b360 authored by Thomas Petazzoni's avatar Thomas Petazzoni
Browse files

Merge tag 'marvell-armadaxp-smp-for-3.8' of... 

Merge tag 'marvell-armadaxp-smp-for-3.8' of github.com:MISL-EBU-System-SW/mainline-public into mevbu-dt-additions

SMP support for Armada XP

The purpose of this series is to add the SMP support for the Armada XP
SoCs. Beside the SMP support itself brought by the last 3 commits,
this series also adds the support for the coherency fabric unit and
the power management service unit.

The coherency fabric is responsible for ensuring hardware coherency
between all CPUs and between CPUs and I/O masters. This unit is also
available for Armada 370 and will be used in an incoming patch set
for hardware I/O cache coherency.

The power management service unit is responsible for powering down and
waking up CPUs and other SOC units.

Conflicts:
	arch/arm/mach-mvebu/armada-370-xp.c
parents a79cfde1 45f5984a

Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt

+9 −3
Original line number Diff line number Diff line
@@ -6,9 +6,15 @@ Required properties: 
- interrupt-controller: Identifies the node as an interrupt controller.

- #interrupt-cells: The number of cells to define the interrupts. Should be 1.

  The cell is the IRQ number



- reg: Should contain PMIC registers location and length. First pair

  for the main interrupt registers, second pair for the per-CPU

  interrupt registers

  interrupt registers. For this last pair, to be compliant with SMP

  support, the "virtual" must be use (For the record, these registers

  automatically map to the interrupt controller registers of the

  current CPU)







Example:
@@ -18,6 +24,6 @@ Example: 
              #address-cells = <1>;

              #size-cells = <1>;

              interrupt-controller;

              reg = <0xd0020000 0x1000>,

                    <0xd0021000 0x1000>;

              reg = <0xd0020a00 0x1d0>,

                    <0xd0021070 0x58>;

        };

Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt

0 → 100644
+20 −0
Original line number Diff line number Diff line 
Power Management Service Unit(PMSU)

-----------------------------------

Available on Marvell SOCs: Armada 370 and Armada XP



Required properties:



- compatible: "marvell,armada-370-xp-pmsu"



- reg: Should contain PMSU registers location and length. First pair

  for the per-CPU SW Reset Control registers, second pair for the

  Power Management Service Unit.



Example:



armada-370-xp-pmsu@d0022000 {

	compatible = "marvell,armada-370-xp-pmsu";

	reg = <0xd0022100 0x430>,

	      <0xd0020800 0x20>;

};

Documentation/devicetree/bindings/arm/coherency-fabric.txt

0 → 100644
+16 −0
Original line number Diff line number Diff line 
Coherency fabric

----------------

Available on Marvell SOCs: Armada 370 and Armada XP



Required properties:



- compatible: "marvell,coherency-fabric"

- reg: Should contain,coherency fabric registers location and length.



Example:



coherency-fabric@d0020200 {

	compatible = "marvell,coherency-fabric";

	reg = <0xd0020200 0xb0>;

};

arch/arm/boot/dts/armada-370-xp.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -36,6 +36,11 @@ 
	      interrupt-controller;

	};



	coherency-fabric@d0020200 {

		compatible = "marvell,coherency-fabric";

		reg = <0xd0020200 0xb0>;

	};



	soc {

		#address-cells = <1>;

		#size-cells = <1>;

arch/arm/boot/dts/armada-xp.dtsi

+7 −1
Original line number Diff line number Diff line
@@ -24,7 +24,13 @@ 


	mpic: interrupt-controller@d0020000 {

	      reg = <0xd0020a00 0x1d0>,

		    <0xd0021870 0x58>;

		    <0xd0021070 0x58>;

	};



	armada-370-xp-pmsu@d0022000 {

		compatible = "marvell,armada-370-xp-pmsu";

		reg = <0xd0022100 0x430>,

		      <0xd0020800 0x20>;

	};



	soc {

CRA Git | Maintained and supported by SUSTech CRA and CCSE