Commit 1103d3a5 authored by Jose Abreu's avatar Jose Abreu Committed by David S. Miller
Browse files

net: stmmac: dwmac4: Also use TBU interrupt to clean TX path 



TBU interrupt is a normal interrupt and can be used to trigger the
cleaning of TX path. Lets check if it's active in DMA interrupt handler.

While at it, refactor a little bit the function:
	- Don't check if RI is enabled because at function exit we will
	  only clear the interrupts that are enabled so, no event will be
	  missed.

In my tests with GMAC5 this increased performance.

Signed-off-by: default avatarJose Abreu <joabreu@synopsys.com>
Cc: Joao Pinto <jpinto@synopsys.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 4ccb4585

drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c

+7 −17
Original line number Diff line number Diff line
@@ -124,9 +124,9 @@ void dwmac4_disable_dma_irq(void __iomem *ioaddr, u32 chan) 
int dwmac4_dma_interrupt(void __iomem *ioaddr,

			 struct stmmac_extra_stats *x, u32 chan)

{

	int ret = 0;



	u32 intr_status = readl(ioaddr + DMA_CHAN_STATUS(chan));

	u32 intr_en = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));

	int ret = 0;



	/* ABNORMAL interrupts */

	if (unlikely(intr_status & DMA_CHAN_STATUS_AIS)) {
@@ -151,16 +151,11 @@ int dwmac4_dma_interrupt(void __iomem *ioaddr, 
	if (likely(intr_status & DMA_CHAN_STATUS_NIS)) {

		x->normal_irq_n++;

		if (likely(intr_status & DMA_CHAN_STATUS_RI)) {

			u32 value;



			value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan));

			/* to schedule NAPI on real RIE event. */

			if (likely(value & DMA_CHAN_INTR_ENA_RIE)) {

			x->rx_normal_irq_n++;

			ret |= handle_rx;

		}

		}

		if (likely(intr_status & DMA_CHAN_STATUS_TI)) {

		if (likely(intr_status & (DMA_CHAN_STATUS_TI |

					  DMA_CHAN_STATUS_TBU))) {

			x->tx_normal_irq_n++;

			ret |= handle_tx;

		}
@@ -168,12 +163,7 @@ int dwmac4_dma_interrupt(void __iomem *ioaddr, 
			x->rx_early_irq++;

	}



	/* Clear the interrupt by writing a logic 1 to the chanX interrupt

	 * status [21-0] expect reserved bits [5-3]

	 */

	writel((intr_status & 0x3fffc7),

	       ioaddr + DMA_CHAN_STATUS(chan));



	writel(intr_status & intr_en, ioaddr + DMA_CHAN_STATUS(chan));

	return ret;

}

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