Commit 11000300 authored by Neil Armstrong's avatar Neil Armstrong Committed by Steven Price
Browse files

drm/panfrost: add amlogic reset quirk callback 



The T820, G31 & G52 GPUs integrated by Amlogic in the respective GXM,
G12A/SM1 & G12B SoCs needs a quirk in the PWR registers at the GPU reset
time.

Since the Amlogic's integration of the GPU cores with the SoC is not
publicly documented we do not know what does these values, but they
permit having a fully functional GPU running with Panfrost.

Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
[Steven: Fix typo in commit log]
Reviewed-by: default avatarSteven Price <steven.price@arm.com>
Reviewed-by: default avatarAlyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: default avatarSteven Price <steven.price@arm.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200916150147.25753-3-narmstrong@baylibre.com
parent 91e89097

drivers/gpu/drm/panfrost/panfrost_gpu.c

+11 −0
Original line number Diff line number Diff line
@@ -76,6 +76,17 @@ int panfrost_gpu_soft_reset(struct panfrost_device *pfdev) 
	return 0;

}



void panfrost_gpu_amlogic_quirk(struct panfrost_device *pfdev)

{

	/*

	 * The Amlogic integrated Mali-T820, Mali-G31 & Mali-G52 needs

	 * these undocumented bits in GPU_PWR_OVERRIDE1 to be set in order

	 * to operate correctly.

	 */

	gpu_write(pfdev, GPU_PWR_KEY, GPU_PWR_KEY_UNLOCK);

	gpu_write(pfdev, GPU_PWR_OVERRIDE1, 0xfff | (0x20 << 16));

}



static void panfrost_gpu_init_quirks(struct panfrost_device *pfdev)

{

	u32 quirks = 0;

drivers/gpu/drm/panfrost/panfrost_gpu.h

+2 −0
Original line number Diff line number Diff line
@@ -16,4 +16,6 @@ int panfrost_gpu_soft_reset(struct panfrost_device *pfdev); 
void panfrost_gpu_power_on(struct panfrost_device *pfdev);

void panfrost_gpu_power_off(struct panfrost_device *pfdev);



void panfrost_gpu_amlogic_quirk(struct panfrost_device *pfdev);



#endif

drivers/gpu/drm/panfrost/panfrost_regs.h

+4 −0
Original line number Diff line number Diff line
@@ -51,6 +51,10 @@ 
#define GPU_STATUS			0x34

#define   GPU_STATUS_PRFCNT_ACTIVE	BIT(2)

#define GPU_LATEST_FLUSH_ID		0x38

#define GPU_PWR_KEY			0x50	/* (WO) Power manager key register */

#define  GPU_PWR_KEY_UNLOCK		0x2968A819

#define GPU_PWR_OVERRIDE0		0x54	/* (RW) Power manager override settings */

#define GPU_PWR_OVERRIDE1		0x58	/* (RW) Power manager override settings */

#define GPU_FAULT_STATUS		0x3C

#define GPU_FAULT_ADDRESS_LO		0x40

#define GPU_FAULT_ADDRESS_HI		0x44

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