can: ti_hecc: keep MIM and MD set (10f5d55d) · Commits · 戴 / test

The HECC_CANMIM is set in the xmit path and cleared in the interrupt. Since this is done with a read, modify, write action the register might end up with some more MIM enabled then intended, since it is not protected. That doesn't matter at all, since the tx interrupt disables the mailbox with HECC_CANME (while holding a spinlock). So lets just always keep MIM set. While at it, since the mailbox direction never changes, don't set it every time a message is send, ti_hecc_reset() already sets them to tx. Signed-off-by:

Jeroen Hofstee <jhofstee@victronenergy.com> Signed-off-by:

Marc Kleine-Budde <mkl@pengutronix.de>

drivers/net/can/ti_hecc.c

+3 −3

Original line number	Diff line number	Diff line
		@@ -382,6 +382,9 @@ static void ti_hecc_start(struct net_device *ndev)
		hecc_set_bit(priv, HECC_CANMIM, mbx_mask);
		}

		/* Enable tx interrupts */
		hecc_set_bit(priv, HECC_CANMIM, BIT(HECC_MAX_TX_MBOX) - 1);

		/* Prevent message over-write & Enable interrupts */
		hecc_write(priv, HECC_CANOPC, HECC_SET_REG);
		if (priv->use_hecc1int) {
		@@ -511,8 +514,6 @@ static netdev_tx_t ti_hecc_xmit(struct sk_buff skb, struct net_device ndev)
		hecc_set_bit(priv, HECC_CANME, mbx_mask);
		spin_unlock_irqrestore(&priv->mbx_lock, flags);

		hecc_clear_bit(priv, HECC_CANMD, mbx_mask);
		hecc_set_bit(priv, HECC_CANMIM, mbx_mask);
		hecc_write(priv, HECC_CANTRS, mbx_mask);

		return NETDEV_TX_OK;
		@@ -676,7 +677,6 @@ static irqreturn_t ti_hecc_interrupt(int irq, void *dev_id)
		mbx_mask = BIT(mbxno);
		if (!(mbx_mask & hecc_read(priv, HECC_CANTA)))
		break;
		hecc_clear_bit(priv, HECC_CANMIM, mbx_mask);
		hecc_write(priv, HECC_CANTA, mbx_mask);
		spin_lock_irqsave(&priv->mbx_lock, flags);
		hecc_clear_bit(priv, HECC_CANME, mbx_mask);

Admin message