Commit 10f39f04 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-linus-20121009' of git://git.infradead.org/mtd-2.6 

Pull MTD updates from David Woodhouse:

 - Disable broken mtdchar mmap() on MMU systems
 - Additional ECC tests for NAND flash, and some test cleanups
 - New NAND and SPI chip support
 - Fixes/cleanup for SH FLCTL NAND controller driver
 - Improved hardware support for GPMI NAND controller
 - Conversions to device-tree support for various drivers
 - Removal of obsolete drivers (sbc8xxx, bcmring, etc.)
 - New LPC32xx drivers for MLC and SLC NAND
 - Further cleanup of NAND OOB/ECC handling
 - UAPI cleanup merge from David Howells (just moving files, since MTD
   headers were sorted out long ago to separate user-visible from kernel
   bits)

* tag 'for-linus-20121009' of git://git.infradead.org/mtd-2.6: (168 commits)
  mtd: Disable mtdchar mmap on MMU systems
  UAPI: (Scripted) Disintegrate include/mtd
  mtd: nand: detect Samsung K9GBG08U0A, K9GAG08U0F ID
  mtd: nand: decode Hynix MLC, 6-byte ID length
  mtd: nand: increase max OOB size to 640
  mtd: nand: add generic READ ID length calculation functions
  mtd: nand: split simple ID decode into its own function
  mtd: nand: split extended ID decoding into its own function
  mtd: nand: split BB marker options decoding into its own function
  mtd: nand: remove redundant ID read
  mtd: nand: remove unnecessary variable
  mtd: docg4: add missing HAS_IOMEM dependency
  mtd: gpmi: initialize the timing registers only one time
  mtd: gpmi: add EDO feature for imx6q
  mtd: gpmi: do not set the default values for the extra clocks
  mtd: gpmi: simplify the DLL setting code
  mtd: gpmi: add a new field for HW_GPMI_CTRL1
  mtd: gpmi: do not get the clock frequency in gpmi_begin()
  mtd: gpmi: add a new field for HW_GPMI_TIMING1
  mtd: add helpers to get the supportted ONFI timing mode
  ...
parents 72055425 f5cf8f07

Documentation/DocBook/mtdnand.tmpl

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@@ -1216,8 +1216,6 @@ in this page</entry> 
#define	NAND_BBT_LASTBLOCK	0x00000010

/* The bbt is at the given page, else we must scan for the bbt */

#define NAND_BBT_ABSPAGE	0x00000020

/* The bbt is at the given page, else we must scan for the bbt */

#define NAND_BBT_SEARCH		0x00000040

/* bbt is stored per chip on multichip devices */

#define NAND_BBT_PERCHIP	0x00000080

/* bbt has a version counter at offset veroffs */

Documentation/devicetree/bindings/arm/davinci/nand.txt

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* Texas Instruments Davinci NAND



This file provides information, what the device node for the

davinci nand interface contain.



Required properties:

- compatible: "ti,davinci-nand";

- reg : contain 2 offset/length values:

        - offset and length for the access window

        - offset and length for accessing the aemif control registers

- ti,davinci-chipselect: Indicates on the davinci_nand driver which

                         chipselect is used for accessing the nand.



Recommended properties :

- ti,davinci-mask-ale: mask for ale

- ti,davinci-mask-cle: mask for cle

- ti,davinci-mask-chipsel: mask for chipselect

- ti,davinci-ecc-mode: ECC mode valid values for davinci driver:

		- "none"

		- "soft"

		- "hw"

- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.

- ti,davinci-nand-buswidth: buswidth 8 or 16

- ti,davinci-nand-use-bbt: use flash based bad block table support.



Example (enbw_cmc board):

aemif@60000000 {

	compatible = "ti,davinci-aemif";

	#address-cells = <2>;

	#size-cells = <1>;

	reg = <0x68000000 0x80000>;

	ranges = <2 0 0x60000000 0x02000000

		  3 0 0x62000000 0x02000000

		  4 0 0x64000000 0x02000000

		  5 0 0x66000000 0x02000000

		  6 0 0x68000000 0x02000000>;

	nand@3,0 {

		compatible = "ti,davinci-nand";

		reg = <3 0x0 0x807ff

			6 0x0 0x8000>;

		#address-cells = <1>;

		#size-cells = <1>;

		ti,davinci-chipselect = <1>;

		ti,davinci-mask-ale = <0>;

		ti,davinci-mask-cle = <0>;

		ti,davinci-mask-chipsel = <0>;

		ti,davinci-ecc-mode = "hw";

		ti,davinci-ecc-bits = <4>;

		ti,davinci-nand-use-bbt;

	};

};

Documentation/devicetree/bindings/mtd/atmel-nand.txt

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@@ -3,7 +3,9 @@ Atmel NAND flash 
Required properties:

- compatible : "atmel,at91rm9200-nand".

- reg : should specify localbus address and size used for the chip,

	and if availlable the ECC.

	and hardware ECC controller if available.

	If the hardware ECC is PMECC, it should contain address and size for

	PMECC, PMECC Error Location controller and ROM which has lookup tables.

- atmel,nand-addr-offset : offset for the address latch.

- atmel,nand-cmd-offset : offset for the command latch.

- #address-cells, #size-cells : Must be present if the device has sub-nodes
@@ -16,6 +18,15 @@ Optional properties: 
- nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.

  Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",

  "soft_bch".

- atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware.

  Only supported by at91sam9x5 or later sam9 product.

- atmel,pmecc-cap : error correct capability for Programmable Multibit ECC

  Controller. Supported values are: 2, 4, 8, 12, 24.

- atmel,pmecc-sector-size : sector size for ECC computation. Supported values

  are: 512, 1024.

- atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM

  for different sector size. First one is for sector size 512, the next is for

  sector size 1024.

- nand-bus-width : 8 or 16 bus width if not present 8

- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
@@ -39,3 +50,30 @@ nand0: nand@40000000,0 { 
		...

	};

};



/* for PMECC supported chips */

nand0: nand@40000000 {

	compatible = "atmel,at91rm9200-nand";

	#address-cells = <1>;

	#size-cells = <1>;

	reg = < 0x40000000 0x10000000	/* bus addr & size */

		0xffffe000 0x00000600	/* PMECC addr & size */

		0xffffe600 0x00000200	/* PMECC ERRLOC addr & size */

		0x00100000 0x00100000	/* ROM addr & size */

		>;

	atmel,nand-addr-offset = <21>;	/* ale */

	atmel,nand-cmd-offset = <22>;	/* cle */

	nand-on-flash-bbt;

	nand-ecc-mode = "hw";

	atmel,has-pmecc;	/* enable PMECC */

	atmel,pmecc-cap = <2>;

	atmel,pmecc-sector-size = <512>;

	atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;

	gpios = <&pioD 5 0	/* rdy */

		 &pioD 4 0	/* nce */

		 0		/* cd */

		>;

	partition@0 {

		...

	};

};

Documentation/devicetree/bindings/mtd/gpmi-nand.txt

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@@ -12,6 +12,10 @@ Required properties: 
  - interrupt-names : The interrupt names "gpmi-dma", "bch";

  - fsl,gpmi-dma-channel : Should contain the dma channel it uses.



Optional properties:

  - nand-on-flash-bbt: boolean to enable on flash bbt option if not

                       present false



The device tree may optionally contain sub-nodes describing partitions of the

address space. See partition.txt for more detail.

Documentation/devicetree/bindings/mtd/lpc32xx-mlc.txt

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NXP LPC32xx SoC NAND MLC controller



Required properties:

- compatible: "nxp,lpc3220-mlc"

- reg: Address and size of the controller

- interrupts: The NAND interrupt specification

- gpios: GPIO specification for NAND write protect



The following required properties are very controller specific. See the LPC32xx

User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in

Hz, to make them independent of actual clock speed and to provide for good

accuracy:)

- nxp,tcea_delay: TCEA_DELAY

- nxp,busy_delay: BUSY_DELAY

- nxp,nand_ta: NAND_TA

- nxp,rd_high: RD_HIGH

- nxp,rd_low: RD_LOW

- nxp,wr_high: WR_HIGH

- nxp,wr_low: WR_LOW



Optional subnodes:

- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt



Example:



	mlc: flash@200A8000 {

		compatible = "nxp,lpc3220-mlc";

		reg = <0x200A8000 0x11000>;

		interrupts = <11 0>;

		#address-cells = <1>;

		#size-cells = <1>;



		nxp,tcea-delay = <333333333>;

		nxp,busy-delay = <10000000>;

		nxp,nand-ta = <18181818>;

		nxp,rd-high = <31250000>;

		nxp,rd-low = <45454545>;

		nxp,wr-high = <40000000>;

		nxp,wr-low = <83333333>;

		gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */



		mtd0@00000000 {

			label = "boot";

			reg = <0x00000000 0x00064000>;

			read-only;

		};



		...



	};

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