DM9000B: Fix PHY power for network down/up (108f518c) · Commits · 戴 / test

DM9000 revision B needs 1 ms delay after PHY power-on. PHY must be powered on by writing 0 into register DM9000_GPR before all other settings will change (see Davicom spec and example code). Remember, that register DM9000_GPR was not changed by reset sequence. Without this fix the FIFO is out of sync and sends wrong data after sequence of "ifconfig ethX down ; ifconfig ethX up". Signed-off-by:

David S. Miller <davem@davemloft.net>

drivers/net/dm9000.c

+4 −3

Original line number	Diff line number	Diff line
		@@ -802,10 +802,7 @@ dm9000_init_dm9000(struct net_device *dev)
		/* Checksum mode */
		dm9000_set_rx_csum_unlocked(dev, db->rx_csum);

		/* GPIO0 on pre-activate PHY */
		iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */
		iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */
		iow(db, DM9000_GPR, 0); /* Enable PHY */

		ncr = (db->flags & DM9000_PLATF_EXT_PHY) ? NCR_EXT_PHY : 0;

		@@ -1194,6 +1191,10 @@ dm9000_open(struct net_device *dev)
		if (request_irq(dev->irq, dm9000_interrupt, irqflags, dev->name, dev))
		return -EAGAIN;

		/* GPIO0 on pre-activate PHY, Reg 1F is not set by reset */
		iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */
		mdelay(1); /* delay needs by DM9000B */

		/* Initialize DM9000 board */
		dm9000_reset(db);
		dm9000_init_dm9000(dev);

Admin message